X76F400 Flash Datasheet

X76F400 Datasheet, PDF, Equivalent


Part Number

X76F400

Description

Secure Serial Flash

Manufacture

Xicor

Total Page 14 Pages
Datasheet
Download X76F400 Datasheet


X76F400
4K
X76F400
512 x 8 bit
Secure SerialFlash
FEATURES
• 64-bit password security
• One array (496 bytes) two passwords (16 bytes)
—Read password
—Write password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of the array
• 32-bit response to reset (RST input)
• 8 byte sector write mode
• 1MHz clock rate
• 2-wire serial interface
• Low power CMOS
—2.5 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead, SOIC,TSSOP
DESCRIPTION
The X76F400 is a password access security supervi-
sor, containing one 3968-bit Secure SerialFlash array.
Access to the memory array can be controlled by two
64-bit passwords. These passwords protect read and
write operations of the memory array.
The X76F400 features a serial interface and software
protocol allowing operation on a popular 2-wire bus.
The bus signals are a clock input (SCL) and a bi-direc-
tional data input and output (SDA).
The X76F400 also features a synchronous response
to reset, providing an automatic output of a hard-wired
32-bit data stream, thereby meeting the industry stan-
dard for memory cards.
The X76F400 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
BLOCK DIAGRAM
SCL
SDA
Interface
Logic
RST
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REV 1.0 7/5/00
Data Transfer
Array Access
Enable
Password Array
and Password
Verification Logic
ISO Reset
Response Register
Retry Counter
Erase Logic
496 Byte
EEPROM Array
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www.xicor.com
Characteristics subject to change without notice. 1 of 14

X76F400
X76F400
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. Dur-
ing a read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Reset (RST)
RST is a device reset pin. When RST is pulsed high,
the X76F400 will output 32 bits of fixed data, which
conforms to the standard for “synchronous response-
to-reset.” The part must not be in a write cycle for the
response-to-reset to occur. See Figure 7. If power is
interrupted during the response-to-reset, the response-
to-reset will be aborted and the part will return to the
standby state. The response to reset is “mask pro-
grammable” only!
DEVICE OPERATION
The X76F400 memory array consists of 62 8-byte sec-
tors. Read or write access to the array always begins at
the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8 bytes.
There are two primary modes of operation for the
X76F400; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8-
byte passwords.
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0.’
The user must perform ACK polling to determine the
validity of the password, prior to starting a data transfer
(see Acknowledge Polling). Only after the correct pass-
word is accepted, and an ACK polling has been
performed, can the data transfer occur. See Figure 1.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “response-to-reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F400 is in a nonvolatile write cycle a “no
ACK” (SDA = High) response will be issued in
response to loading of the command byte. If a stop is
issued prior to the nonvolatile write cycle, the write
operation will be terminated; the part will then reset
and enter into a standby mode.
(The basic sequence is illustrated in Figure 1.)
PIN NAMES
Symbol
SDA
SCL
RST
VCC
VSS
NC
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
VSS
NC
SDA
NC
SOIC
18
27
36
45
VCC
RST
SCL
NC
VCC
NC
NC
VSS
TSSOP
18
27
36
45
RST
SCL
SDA
NC
After each transaction is completed, the X76F400 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
REV 1.0 7/5/00
www.xicor.com
Characteristics subject to change without notice. 2 of 14


Features 4K X76F400 Secure SerialFlash 512 x 8 bit FEATURES • 64-bit password secur ity • One array (496 bytes) two passw ords (16 bytes) —Read password —Wri te password • Programmable passwords • Retry counter register —Allows 8 tries before clearing of the array • 32-bit response to reset (RST input) 8 byte sector write mode • 1MHz clo ck rate • 2-wire serial interface • Low power CMOS —2.5 to 5.5V operatio n —Standby current less than 1µA — Active current less than 3 mA • High reliability endurance: —100,000 write cycles • Data retention: 100 years Available in: —8-lead, SOIC,TSSOP DESCRIPTION The X76F400 is a password access security supervisor, containing one 3968-bit Secure SerialFlash array. Access to the memory array can be contr olled by two 64-bit passwords. These pa sswords protect read and write operatio ns of the memory array. The X76F400 fea tures a serial interface and software p rotocol allowing operation on a popular 2-wire bus. The bus signals are a clock input (SCL) and a bi-dir.
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