/ SRAM. MB84VD23381EF Datasheet

MB84VD23381EF SRAM. Datasheet pdf. Equivalent

Part MB84VD23381EF
Description Flash Memory / SRAM
Feature ( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50301-1E Stacked MCP (M.
Manufacture Fujitsu Media Devices
Datasheet
Download MB84VD23381EF Datasheet

( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR D MB84VD23381EF Datasheet
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MB84VD23381EF
( DataSheet : www.DataSheet4U.com )
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50301-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64 M (×16) FLASH MEMORY &
16 M (×16) Mobile FCRAMTM
MB84VD23381EF-85
s FEATURES
• Power Supply Voltage of 2.7 V to 3.0 V for FCRAM
Power Supply Voltage of 2.7 V to 3.3 V for Flash
High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (FCRAM)
s PRODUCT LINE UP
(Continued)
Flash Memory
FCRAM*
Max Address Access Time (ns)
VCCf = 2.7 V to 3.3 V
85
VCCs = 2.7 V to 3.0 V
85
Max CE Access Time (ns)
85
85
Max OE Access Time (ns)
35
60
* : Both VCCf and VCCs must be the same level when either part is being accessed and VCCf can be 2.4 V during
standby state.
s PACKAGE
101-ball plastic FBGA
www.DataSheet4U.com
(BGA-101P-M01)
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MB84VD23381EF
MB84VD23381EF-85
(Continued)
Operating Temperature
30 °C to +85 °C
Package 101-ball FBGA
FLASH MEMORY
Simultaneous Read/Write Operations (FlexBankTM)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, then read immediately and simultaneously read from the other
bank Zero latency between read and write operations
Read-while-erase
Read-while-program
Minimum 100,000 Write/Erase Cycles
Sector Erase Architecture
Sixteen 4 K words and one hundred twenty-six 32 K word sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
Low VCC Write Inhibit 2.5 V
Hidden ROM (Hi-ROM) Region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At VIL, allows protection of “outermost” 2 × 8 K bytes on both ends of boot secctors, regardless of sector
protection/unprotection status.
At VIH, allows removal of boot sector protection
At VACC, program time will be reduced by 40 %.
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL640E” datasheet in detailed function
FCRAMTM
Power Dissipation
Operating : 20 mA Max
Standby : 100 µA Max
Power Down : 10 µA Max
• Power Down Control by CE2s
• Byte Write Control : LBs (DQ7-DQ0) , UBs (DQ15-DQ8)
FlexBankTM is a trademark of Fujitsu Limited, Japan.
FCRAMTMTM is a trademark of Fujitsu Limited, Japan.
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