Burst SRAM. GVT7C1325A Datasheet
( DataSheet : www.DataSheet4U.com )
256K x 18 Synchronous Flow-Through Burst SRAM
• Fast access times: 7.5 and 8 ns
• Fast clock speed: 117 and 100 MHz
• Provide high-performance 2-1-1-1 access rate
• Fast OE access times: 4.0 ns
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
• Automatic power-down for portable applications
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1325A/GVT71256E18 SRAM integrates
262,144x18 SRAM cells with advanced synchronous periph-
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
The CY7C1325A/GVT71256E18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PC™ systems and for systems that benefit from a wide syn-
chronous data bus.
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05118 Rev. **
Revised September 12, 2001
256K x 18 (CY7C1325A/GVT71256E18) Functional Block Diagram
Power Down Logic
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05118 Rev. **
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