SDRAM Module. P8M648YL9 Datasheet

P8M648YL9 Module. Datasheet pdf. Equivalent

Part P8M648YL9
Description (P8M644YL9 / P8M648YL9) 8M/16M x 64 DIMM SDRAM Module
Feature 4'.+/+0#4; SDRAM MODULE Features: • • • • • • • • • • PC100 and PC133 - compatible JEDEC - Standard.
Manufacture SpecTek
Datasheet
Download P8M648YL9 Datasheet

4'.+/+0#4; SDRAM MODULE Features: • • • • • • • • • • PC100 P8M648YL9 Datasheet
Recommendation Recommendation Datasheet P8M648YL9 Datasheet




P8M648YL9
SDRAM MODULE
4'.+/+0#4;
P8M644YL9, P16M648YL9
8M, 16M x 64 DIMM
Features:
PC100 and PC133 - compatible
JEDEC - Standard 168-pin , dual in-line memory module
(DIMM).
TSOP components.
Single 3.3v +.3v power supply.
Nonbuffered fully synchronous; all signals measured on
positive edge of system clock.
Internal pipelined operation; column address can be
changed every clock cycle.
Quad internal banks for hiding row access/precharge.
64ms 4096 cycle refresh.
All inputs, outputs, clocks LVTTL compatible.
Options:
4 - 8Mx16 SDRAM TSOP
8 - 8Mx16 SDRAM TSOP
Part Number:
P8M644YL9-XX
P16M648YL9-XX
KEY DIMM MODULE TIMING PARAMETERS
Module
Component Clock CAS Latency
Marking Marking
Freq
-100CL3A -8A
100MHZ
3
-133CL3A -75A
133MHZ
3
GENERAL DESCRIPTION
The P8M644YL9 and P16M648YL9 are high performance
dynamic random-access 64MB and 128MB modules
respectively. These modules are organized in a x64
configuration, and utilize dual bank architecture with a
synchronous interface. All signals are registered on the
positive edge of the clock signals CK0 through CK3. Read and
write accesses to the SDRAM are burst oriented; accesses
start at a location and continue for a programmed number of
locations in a sequence. Accesses begin with an ACTIVE
command, which is followed by a READ or WRITE command.
ABSOLUTE MAXIMUM RATINGS:
Voltage on Vcc Supply relative to Vss...................-1 to +4.6V
Operating Temperature TA (Ambient) .............25 ° to +70 °C
Storage Temperature ......................................-55 to +125 °C
Power Dissipation……………………………………4 or 8 W
Short Circuit Output Current……………………….….50 mA
Stresses beyond these may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at or beyond these conditions is not implied.
Exposure to these conditions for extended periods may affect
reliability.
PIN ASSIGNMENT (Front View)
168-PIN DIMM
Pin Name Pin Name
1 Vss 43 Vss
2
DQ0
44
DU
3 DQ1 45 S2#
4
DQ2
46 DQMB2
5
DQ3
47 DQMB3
6
Vcc 48
DU
7
DQ4
49
Vcc
8
DQ5
50
NC
9
DQ6
51
NC
10 DQ7 52
NC
11 DQ8 53
NC
12 Vss 54 Vss
13 DQ9 55 DQ16
14
DQ10
56
DQ17
15
DQ11
57
DQ18
16
DQ12
58
DQ19
17
DQ13
59
Vcc
18 Vcc 60 DQ20
19
DQ14
61
NC
20
DQ15
62
NC
21 NC 63 CKE1
22 NC 64 Vss
23 Vss 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 Vcc 68 Vss
27 WE# 69 DQ24
28 DQMB0 70
DQ25
29 QQMB1 71
DQ26
30 SO# 72 DQ27
31 DU 73 Vcc
32 Vss 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 Vss
37 A8 79 CK2
38 A10/AP 80
NC
39 BA1 81 NC
40 Vcc 82 SDA
41 Vcc 83 SCL
42 CK0 84 Vcc
Pin Name Pin Name
85 Vss 127 Vss
86 DQ32 128 CKE0
87
DQ33
129
S3#
88
DQ34
130 DQMB6
89
DQ35
131 DQMB7
90 Vcc 132 RFU
91
DQ36
133
Vcc
92
DQ37
134
NC
93
DQ38
135
NC
94
DQ39
136
NC
95
DQ40
137
NC
96 Vss 138 Vss
97 DQ41 139 DQ48
98 DQ42 140 DQ49
99 DQ43 141 DQ50
100 DQ44 142 DQ51
101 DQ45 143
Vcc
102 Vcc 144 DQ52
103 DQ46 145
NC
104 DQ47 146
NC
105 NC 147 NC
106 NC 148 Vss
107 Vss 149 DQ53
108 NC 150 DQ54
109 NC 151 DQ55
110 Vcc 152 Vss
111 CAS# 153 DQ56
112 DQMB4 154
DQ57
113 DQMB5 155
DQ58
114 S1# 156 DQ59
115 RAS# 157
Vcc
116 Vss 158 DQ60
117 A1 159 DQ61
118 A3 160 DQ62
119 A5 161 DQ63
120 A7 162 Vss
121 A9 163 CK3
122 BA0 164 NC
123 A11 165 SA0
124 Vcc 166 SA1
125 CK1 167 SA2
126 RFU 168 Vcc
__________________________________________________________________________________________________
P8M644YL9, P16M648YL9
1 SpecTek reserves the right to change products
Rev: 8/2/00
or specifications without notice. ©2000 SpecTek



P8M648YL9
P8M644YL9, P16M648YL9
CAPACITANCE: (This parameter is sampled. VCC = +3.3V m 0.3V; f = 1 MHz)
Parameter
Symbol
Input Capacitance: A0 - A11, BAO-BA1, RAS#, CAS#, WE#,
Input Capacitance: S0#-S3#, CK0-CK3
Input Capacitance: CKE0, CKE1,
Input Capacitance: DQMB0#, DQMB7
Input Capacitance: SQL, SA0-SA2
Input/Output Capacitance: DQ0-DQ63, SDA
Cl1
Cl2
Cl3
Cl4
Cl5
CIO
Max
64MB 128MB
25 45
15 25
25 45
8 15
66
10 15
Units
pF
pF
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Parameter
Symbol
Min
Supply Voltage
Vcc/Vccq
3.0
Input High (Logic 1) Voltage, All inputs
Input Low (Logic 0) Voltage, All inputs
Input Leakage Current Any input = 0V < VIN < Vcc
All other pins not under test = 0V
Output Leakage Current DQs are disabled; 0V < VOUT < VccQ
Output High Voltage (IOUT = -4 mA)
Output Low Voltage (IOUT = 4 mA)
VIH 2.0
VIL -0.3
II -10
I2 -20
I3 -30
IOZ -20
VOH 2.4
VOL
Max
3.6
Vcc + .3
0.8
10
20
30
20
0.4
Units
V
V
V
uA
uA
V
V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vcc = 3.3V ± 10%V, Temp. = 25° to 70 °C
Supply Current
OPERATING CURRENT: ACTIVE mode, burst = 2,
READ or WRITE, tRC = tRC (MIN), CAS latency = 3
CL = 2
CL = 3
Symbol
Icc1
Icc1
64MB
128MB
64MB
128MB
-75A
N/A
580
1150
-8A
N/A
565
1120
Units
mA
mA
Notes
1, 2, 3
1, 2, 3
STANDBY CURRENT: POWER-DOWN mode, CKE tCK =
= LOW, no accesses in progress
15ns
Icc2 64MB 36
128MB 72
36 mA
72
CLK =
LOW
Icc2 64MB 36
128MB 72
36 mA
72
STANDBY CURRENT: CS# = HIGH, CKE = HIGH,
tCK = 15ns, both banks idle
Icc3 64MB 280
128MB 560
240 mA
480
3, 4
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, tCK = 15ns, Icc4
64MB 240
200 mA
3, 4
both banks active after tRCD met, no accesses in progress.
128MB 480
400
OPERATING CURRENT: BURST mode after tRCD
met, continuous burst, READ, WRITE, tCK > tCK.
CL = 2
Icc5 64MB N/A N/A mA 1, 2, 3
128MB
MIN, other bank active
CL = 3
Icc5 64MB 600 560 mA 1, 2, 3
128MB 1200 1120
AUTO REFRESH CURRENT tRC > tRC (MIN)
CL = 2
Icc6 64MB N/A N/A mA 1, 2, 3
128MB
CL = 3
Icc6 64MB 1000 1000 mA 1, 2, 3
128MB 2000 2000
NOTES:
1. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
2. The Icc current will decrease as the CAS latency is reduced. This is because maximum cycle rate is slower as CAS latency is
reduced.
3. Address transitions average one transition every 30ns.
4. Other input signals are allowed to transition no more than once in any 30ns period.
__________________________________________________________________________________________________
P8M644YL9, P16M648YL9
2 SpecTek reserves the right to change products
Rev: 5/14/00
or specifications without notice. ©2000 SpecTek





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