Gate Arrays. CLA60000 Datasheet

CLA60000 Arrays. Datasheet pdf. Equivalent

Part CLA60000
Description Channel Less CMOS Gate Arrays
Feature ( DataSheet : www.DataSheet4U.com ) CLA60000 Series Channel less CMOS Gate Arrays This new family .
Manufacture Zarlink Semiconductor
Datasheet
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( DataSheet : www.DataSheet4U.com ) CLA60000 Series Channel CLA60000 Datasheet
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CLA60000
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CLA60000 Series
Channel less CMOS Gate Arrays
This new family of gate arrays uses many innovative
techniques to achieve 110K gates per chip with
system clock speeds of up to 70MHz. The
combination of high speed, high gate complexity and
low power operation places Zarlink Semiconductor
at the forefront of ASIC capability.
General Description
The CLA60000 gate array family is Zarlink
Semiconductor’s fifth-generation CMOS gate array
product. These arrays allow even higher integration
densities at enhanced system clock rates as need for
many of today’s system applications.
The largest array in the family at 110K gates offers a
tenfold increase in raw gate availability then
channelled gate arrays. In addition, many new
designs features have been incorporated such as
analog functionality, slew rate output control, and
intermediate I/O buffering for optimum data transfer
through peripheral cells.
Also, the low-power characteristics of Zarlink
Semiconductor CMOS processing have been
incorporated in these arrays, easing the thermal
management problems associated with complex
designs of 20,000 gates and above.
Features
• Channel less arrays to 110,000 gates
• 1.4 micron dual layer metal silicon CMOS
process
• Typical Gate Delays of 700ps (NAND2)
• Comprehensive cell library including microcells,
macrocells, and paracells
• Power distribution optimized for maximum noise
immunity
• Slew controlled outputs with up to 24mA drivers
• Fully supported by design software (PDS2) and
popular workstations
• Very high latch up immunity
Figure 1 - CLA60000 Chip Microplot
All CLA60000 arrays have the same construction. A
core of uncommitted transistors is arranged for
optimum connection as logic functions and
surrounded by uncommitted peripheral (I/O) circuitry.
The channel less array architecture is an important
feature - the absence of discrete wiring channels
increases flexibility, reduces track capacitance whilst
significantly increasing transistor sizes for improved
logic performance.
The construction of the basic building blocks have
been planned to support basic logic functions, macro
functions, and core memory functions (RAM and
ROM) with high routability. Logic programmability is
given by dual level metal, with interconnecting vias,
plus a forth level of programmability (contacts).
The overall architecture of these gate arrays has
been designed to exploit many new and emerging
developments in CAD tools. Increasing demands are
now being made for design tools which are faster,
easier to use, and more accurate. The Zarlink
Semiconductor Design System (PDS2) allows full
control over all aspects of design including logic
capture, simulation and layout.
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CLA60000
CLA60000 Series
Product Range
The CLA60000 product range is shown below.
Actual gate utilization can be typically 40-70% of the
uncommitted gate count depending on circuit
structure.
Product
CLA61XXX
CLA62XXX
CLA63XXX
CLA64XXX
CLA65XXX
CLA66XXX
CLA67XXX
CLA68XXX
Uncommitted
Gate Count
2040
5488
10608
19928
35784
55616
80560
110112
Pads
Including
Power
40
64
88
120
160
200
240
280
Complete rows of array elements can be used as
routing channels to conform to the earlier channeled
Zarlink Semiconductor arrays or, if desired, compact
hierarchical logic blocks and localized routing areas
can be defined like a cell based design layout. The
array structure has been designed to be totally
flexible in architecture with the distribution of logic
blocks and routing channels being definable by the
designer.
I/O Buffer Arrangement
The I/O buffers are the interface to external circuitry
and are therefore required to be robust and flexible.
The inputs and outputs can withstand electro-static
discharges, are not susceptible to latch up (an
inherent CMOS problem) and provide the designer
with multiple interface options.
IB1
IB2
Intermediate
Buffers
Core Arrangement
A four transistor (2 NMOS and 2 PMOS) groups
forms the basis of the core array. This array element
is repeated in a regular fashion over the complete
core area to give a ‘Full Field’ (sea-of-gates) array.
The unique design of the basic four transistor cells
give the Zarlink Semiconductor arrays a major
advantage over all competitors. Thesilicon layout
has been configured so that the basic logic cells, flip-
flops and large hierarchical cells can be
interconnected easily with through-cell routing
channels. It also ensures that an optimum overall
data flow and control signal distribution scheme is
possible.
VDD
Supply
OP1
OP2
IP
Output
Drivers
Bonding
pad
Figure 3 - I/O Block
The CLA60000 I/O buffers contain all the
components for static protection, input pull-up and
pull down resistors, various output drive currents and
input interface signals such as CMOS and TTL. In
addition, the I/O buffer contains all the components
for intermediate buffering stages including Schmitt
triggers, TTL threshold detectors, tristate control,
signal re-timing flip-flops and slew rate control for the
output drivers. Some analog interface cells can also
be implemented using the available components. I/O
buffer locations can also be configured as supply
pads (VDD and VSS).
Programmable
contacts
VSS
Supply
Figure 2 - Array Core Cell
2
INPUT
DATA
D
PP
OPT
N N 50pF
PIN
2.5V
Driver
IB2BD
IBSK1
IBSK2
IBSK3
Delay
Delay (nsec)
4.64
5.50
6.41
9.15
2.5V
Current Ramp (mA/nSec)
57.2
31.8
17.1
8.7
Figure 4 - Slew Control





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