Gate Arrays. CLA90000 Datasheet

CLA90000 Arrays. Datasheet pdf. Equivalent

Part CLA90000
Description High Density CMOS Gate Arrays
Feature ( DataSheet : www.DataSheet4U.com ) CLA90000 Series High Density CMOS Gate Arrays DS5500 ISSUE 2..
Manufacture Zarlink Semiconductor
Datasheet
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CLA90000
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CLA90000 Series
High Density CMOS Gate Arrays
INTRODUCTZarlinkION
The CLA90000 family of gate arrays from Zarlink Semicon-
ductor consists of 14 fixed-size arrays with the option of
building optimized arrays with up to 1.1 million gates. This
family offers low-power, mixed voltage capability and a high
density silicon architecture. The CLA90000 series is easy
to use with and without synthesis tools and comes with
design utilities to provide customers with a faster time to
market.
FEATURES
I Low power, 0.5µW/MHz/gate at 3V supply (NAND 2
loads)
I High density of 5,425 available gates/mm2
I 3V and 5V I/O capability on the same device
I 150ps gate delay for 2-input NAND with two loads (5V)
I Accurate delay modelling for gates and tracks with sign
off quality CAE design libraries for QuickSim II and
Verilog-XL
I CAD libraries optimized for synthesis
I Up to 512K available gates and 352 pads with fixed
arrays
I Up to 1.1M available gates and 520 pads with optimized
arrays
I Double or triple layer metal on a 0.6µm (drawn) process
I Operation from 2.7V to 5.5V
I Methodologies for low clock skew
I Phase locked loop cells, both gate array variant and
embedded variant with on-chip filter
I Embedded RAM and ROM
I Expanding range of Zarlink SytemBuildersoft and
hard cells for complex functions including 85C30, 8051,
and 8251 devices
I Wide range of packaging options including Ball Grid
Arrays
I Commercial and military pad density options
DS5500
ISSUE 2.0
April 1997
BENEFITS
I Fast Customer Time To Market
- Direct sign-off on industry standard CAE tools
- Comprehensive industry-standard design tool flows
- SystemBuilder™ megacell libraries
- Worldwide design centre support
- Reliable prototype and production delivery
- Two silicon sources
I Cost-effective solutions
- Optimized silicon architecture for excellent silicon
utilization
- Statistical process control for optimum yield
- High quality and reliability, manufactured to MIL STD
883 methods and other industry recognized standards
OVERVIEW
The CLA90000 series product has a number of important
elements that assist designers.
Ease of design
Ease of design is an important feature of this new product,
as shown by the checking and verification utilities built into
the Zarlink design kits. Accurate simulation is essential for
good design, and the Zarlink 5th order pin to pin delay
model algorithms help ensure first time success. Various
design routes and industry-standard systems are avail-
able.
Cell Libraries
Cell libraries are optimized for synthesis and include a
complete range of soft and hard macros. Cells include
basic logic, oscillators, JTAG controllers and macros from
the extensive SystemBuilder™ library such as micropro-
cessors, memories, UARTs, and DSP elements, which
improve time to market through a shorter design cycle.
Embedded custom blocks can be inserted into a gate
array to produce dense memory or other compact high
performance components. Optimized arrays can offer gate
array cycle times if embedded blocks are defined early in
the design cycle.
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CLA90000
Silicon and process
This generation of gate arrays uses a 0.6µm process and
meets its primary objectives of dense architecture and low
power without compromising performance. Packing den-
sity is 5,500 available gates per mm2, with utilization for
three-layer metal typically exceeding 70% (random logic).
Power consumption is low with both 5V and 3V supplies,
reaching 0.5µW/MHz/gate at 3V with two gate loads.
Service
The service Zarlink offers to customers encompasses
product guidance from a marketing team, engineering
expertise, including design advice and in-depth knowledge
of CAE tools, through to fast delivery and world class qual-
ity and reliability standards.
ARRAY SIZES
CLA90000 consists of a series of fixed, embedded and
optimized arrays that can be combined as shown below.
Fixed arrays
Embedded
memory or
macros
Optimized arrays
Standard, fixed array sizes are prefabricated and appropri-
ate probe cards are available for fast turn around and low
cost.
For a design with a large memory (2k bits or more) or
when an embedded macro like an ARM RISC micropro-
cessor is required, all device layers can be fabricated. An
embedded array uses the fixed array bases but with a sec-
tion of the array removed to make space for the custom
block. Optimized arrays are customized to the application,
can be built with the required number of pads or gates, and
can also include embedded cells.
Optimized arrays are most often used in medium- to high-
volume applications where the larger engineering cost is
balanced by lower production pricing. For high volume
devices, an optimized array can be generated at Zarlink
using automated tools. The Zarlink Design Centres can
advise on the best options, in terms of fixed gate arrays
and standard cells, for a given design.
Embedded and optimized arrays are as easy to design
with as the fixed array bases, and have similar prototyping
times provided custom cell definition or new array size is
decided early in the design.
A wide range of packages is offered for both the fixed and
optimized arrays, and all arrays offer the choice of com-
mercial or military pad density. The lower pad density
meets the need of MIL STD customers in terms of bond
wire spacing specifications.
CLA90000 has a range of fixed array bases to offer a suit-
able array size for most applications, from low to high vol-
ume.
Fixed Gate Arrays
Array
No. of
Gates
Typical Utilization
of Gates
2-layer
metal
3-layer
metal
Number of
Pads
CLA 901
CLA 902
CLA 903
CLA 904
CLA 905
CLA 906
CLA 907
CLA 908
CLA 909
CLA 910
CLA 911
CLA 912
CLA 913
CLA 914
21632
32768
57800
75272
95048
141512
168200
228488
262088
297992
336200
376712
419528
512072
9700
14000
26000
33000
42000
63000
75000
102000
117000
134000
151000
169000
188000
230000
15000
23000
40000
52000
66000
99000
117000
160000
183000
208000
235000
263000
293000
358000
84
100
128
144
160
192
208
240
256
272
288
304
320
352
44
52
64
72
80
96
104
120
128
136
144
152
160
176
Optimized Gate Arrays
Array
Max.
No. of
Gates
Typical Utilization
of Gates
2-layer
metal
3-layer
metal
Max. Number
of Pads
*CLA9XX 114912
8
517000
804000
520
264
* optimized arrays available up to 1.1M gates.
# MIL density pad spacing
2





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