Controller Hub. RGE7500 Datasheet

RGE7500 Hub. Datasheet pdf. Equivalent


Intel RGE7500
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Intel® E7500 Chipset
Datasheet
Intel® E7500 Memory Controller Hub (MCH)
February 2002
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Document Number: 290730-001
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RGE7500 Datasheet
Recommendation RGE7500 Datasheet
Part RGE7500
Description Memory Controller Hub
Feature RGE7500; ( DataSheet : www.DataSheet4U.com ) Intel® E7500 Chipset Datasheet Intel® E7500 Memory Controller H.
Manufacture Intel
Datasheet
Download RGE7500 Datasheet




Intel RGE7500
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intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® E7500 chipset MCH component may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright© 2002, Intel Corporation
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Intel RGE7500
Contents
1 Introduction ................................................................................................................11
1.1 Glossary of Terms ...............................................................................................11
1.2 Reference Documents.........................................................................................12
1.3 Intel® E7500 Chipset System Architecture..........................................................12
1.3.1 Intel® 82801CA I/O Controller Hub 3-S (ICH3-S)...................................13
1.3.2 Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)...................................14
1.4 Intel® E7500 MCH Overview...............................................................................14
1.4.1 Processor System Interface ...................................................................15
1.4.2 Main Memory Interface...........................................................................15
1.4.3 Hub Interface_A (HI_A) ..........................................................................15
1.4.4 Hub Interface_B–D (HI_B–D).................................................................16
1.4.5 MCH Clocking ........................................................................................16
1.4.6 SMBus Interface.....................................................................................16
2 Signal Description ...................................................................................................17
2.1 System Bus Interface Signals .............................................................................19
2.2 DDR Channel A Signals ......................................................................................22
2.3 DDR Channel B Signals ......................................................................................23
2.4 Hub Interface_A Signals......................................................................................24
2.5 Hub Interface_B Signals......................................................................................25
2.6 Hub Interface_C Signals .....................................................................................26
2.7 Hub Interface_D Signals .....................................................................................27
2.8 Clocks, Reset, Power, and Miscellaneous Signals .............................................28
2.9 Pin States During and After Reset ......................................................................28
3 Register Description ...............................................................................................31
3.1 Register Terminology ..........................................................................................31
3.2 Platform Configuration.........................................................................................32
3.3 General Routing Configuration Accesses ...........................................................33
3.3.1 Standard PCI Configuration Mechanism ................................................33
3.3.2 Logical PCI Bus 0 Configuration Mechanism .........................................34
3.3.3 Primary PCI Downstream Configuration Mechanism .............................34
3.3.4 HI_B, HI_C, HI_D Bus Configuration Mechanism ..................................34
3.4 Sticky Registers...................................................................................................35
3.5 I/O Mapped Registers .........................................................................................35
3.5.1 CONF_ADDR—Configuration Address Register ...................................35
3.5.2 CONF_DATA—Configuration Data Register..........................................36
3.6 DRAM Controller Registers (Device 0, Function 0).............................................37
3.6.1 VID—Vendor Identification Register (D0:F0) .........................................38
3.6.2 DID—Device Identification Register (D0:F0) ..........................................38
3.6.3 PCICMD—PCI Command Register (D0:F0) ..........................................39
3.6.4 PCISTS—PCI Status Register (D0:F0) ..................................................40
3.6.5 RID—Revision Identification Register (D0:F0) .......................................41
3.6.6 SUBC—Sub-Class Code Register (D0:F0) ............................................41
3.6.7 BCC—Base Class Code Register (D0:F0).............................................41
3.6.8 MLT—Master Latency Timer Register (D0:F0) ......................................42
Datasheet
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