Clock Source. ICS650R-07C Datasheet

ICS650R-07C Source. Datasheet pdf. Equivalent


Integrated Circuit Systems ICS650R-07C
( DataSheet : www.DataSheet4U.com )
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Description
The ICS650-07C is a low cost, low jitter, high
performance clock synthesizer for networking
applications. Using analog Phase-Locked Loop
(PLL) techniques, the device accepts a 12.5 MHz
or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for
networking chips, PCI devices, SDRAM, and
ASICs. The ICS650-07C outputs all have 0 ppm
synthesis error.
See the MK74CB214, ICS551, and ICS552-01 for
non-PLL buffer devices which produce multiple
low-skew copies of these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay
buffers that can synchronize outputs and other
needed clocks.
Features
• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)
• 12.5 MHz or 25.00 MHz fundamental crystal or
clock input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
Block Diagram
VDD GND
22
2
Output
Buffer
CLKA1
ACS1,0
÷2
Output
Buffer
CLKA2
BCS1,0
2
Clock Synthesis
and Control
Circuitry
Output
Buffer
CLKB1
CCS
÷2
Output
Buffer
CLKB2
12.5 MHz or
25.00 MHz
crystal or clock
X1
X2
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
Output
Buffer
Output
Buffer
CLKC1
CLKC2
REFOUT
OE (all outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
MDS 650-07C A
1
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com
www.DataSheet4U.com


ICS650R-07C Datasheet
Recommendation ICS650R-07C Datasheet
Part ICS650R-07C
Description Networking Clock Source
Feature ICS650R-07C; ( D a t a S h e e t : w w w . D a t a S h e e t 4 U . c o m ) PRELIMINARY INFORMATION ICS650-0.
Manufacture Integrated Circuit Systems
Datasheet
Download ICS650R-07C Datasheet




Integrated Circuit Systems ICS650R-07C
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
For a 25 MHz fundamental crystal or clock input, the following four tables apply :
A Clocks Select Table (outputs in MHz)
ACS1
0
0
0
1
1
1
ACS0
0
M
1
0
M
1
CLKA1
100
Test
75
33.3333
Test
66.6667
CLKA2
off (low)
Test
off (low)
16.6667
Test
33.3333
B Clocks Select Table (outputs in MHz)
BCS1
0
0
0
1
1
1
BCS0
0
M
1
0
M
1
CLKB1
Test
66.6667
100
83.3333
Test
133.3333
CLKB2
Test
33.3333
50
41.6667
Test
66.6667
C Clocks Select Table (outputs in MHz)
CCS CLKC1
0 125
M Test
1 75
CLKC2
125
Test
75
REFOUT
25 MHz
0 = connect directly to GND
M = leave unconnected (automatically self biases to VDD/2)
1 = connect directly to VDD
For a 12.5 MHz crystal or clock input, the following four tables apply :
A Clocks Select Table (outputs in MHz)
ACS1
0
0
0
1
1
1
ACS0
0
M
1
0
M
1
CLKA1
50
Test
37.5
16.6667
Test
33.3333
CLKA2
off (low)
Test
off (low)
8.3333
Test
16.6667
B Clocks Select Table (outputs in MHz)
BCS1
0
0
0
1
1
1
BCS0
0
M
1
0
M
1
CLKB1
Test
33.3333
50
41.6667
Test
66.6667
CLKB2
Test
16.6667
25
20.8333
Test
33.3333
C Clocks Select Table (outputs in MHz)
CCS CLKC1
0 62.5
M Test
1 37.5
CLKC2
62.5
Test
37.5
0 = connect directly to GND
M = leave unconnected (automatically self biases to VDD/2)
1 = connect directly to VDD
REFOUT
12.5 MHz
MDS 650-07C A
2
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com



Integrated Circuit Systems ICS650R-07C
PRELIMINARY INFORMATION
ICS650-07C
Networking Clock Source
Pin Assignment
ACS0
X2
X1/ICLK
VDD
ACS1
GND
CLKC1
CLKC2
CLKB2
CLKB1
1
2
3
4
5
6
7
8
9
10
20 BCS1
19 BCS0
18 REFOUT
17 CLKA1
16 VDD
15 OE
14 GND
13 CLKA2
12 DC
11 CCS
20 pin (150 mil) SSOP
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
ACS0
X2
X1/ICLK
VDD
ACS1
GND
CLKC1
CLKC2
CLKB2
CLKB1
CCS
DC
CLKA2
GND
OE
VDD
CLKA1
REFOUT
BCS0
BCS1
Type
TI
XO
XI
P
I
P
O
O
O
O
TI
-
O
P
I
P
O
O
TI
I
Description
A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 2.
Crystal connection. Connect to a crystal or leave unconnected for a clock input.
Crystal connection. Connect to a fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDD.
A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 2.
Connect to ground.
Clock C output 1. Depends on setting of CCS per table on page 2.
Clock C output 2. Depends on setting of CCS per table on page 2. Same as CLKC1.
Clock B output 2. Depends on setting of BCS1, 0 per table on page 2.
Clock B output 1. Depends on setting of BCS1, 0 per table on page 2.
Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table on page 2.
Don't Connect. Do not connect anything to this pin.
Clock A output 2. Depends on setting of ACS1, 0 per table on page 2.
Connect to ground.
Output Enable. Tri-states all outputs when low.
Connect to +3.3 V or +5 V. Must be same as other VDD.
Clock A output 1. Depends on setting of ACS1, 0 per table on page 2.
Buffered Reference clock Output. Same frequency as crystal or clock input.
B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 2.
B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 2.
Key: TI = tri-level input; XI, XO = crystal connections; I = Input with internal pull-up resistor;
O = Output; P = power supply connection
MDS 650-07C A
3
Revision 101399
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com







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