Flow-Through NtRAM. K7M163625M Datasheet

K7M163625M NtRAM. Datasheet pdf. Equivalent


Samsung semiconductor K7M163625M
( DataSheet : www.DataSheet4U.com )
K7M163625M
K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAMTM
Document Title
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Update ICC & ISB values.
0.2 1. Change tOE from 3.5ns to 4.0ns at -8 .
2. Change tOE from 3.5ns to 4.0ns at -9 .
3. Change tOE from 3.5ns to 4.0ns at -10 .
0.3 1. Change ISB value from 60mA to 80mA at -8.
2. Change ISB value from 50mA to 70mA at -9 .
3. Change ISB value from 40mA to 60mA at -10 .
0.4 1. Changed tCYC from 12ns to 10ns at -9 .
2. Changed DC condition at Icc and parameters
Icc ; from 300mA to 320mA at -8,
from 260mA to 300mA at -9,
from 240mA to 280mA at -10
3. Change pin allocation at 119BGA .
- A4 ; from NC to A .
- B2 ; from A to CS2
- B4 ; from CKE to ADV
- B6 ; from A to CS2
- G4 ; from ADV to A
- H4 ; from NC to WE
- M4 ; from WE toCKE
1.0 1. Final Spec Release.
2.0 Add access time 7.5ns bin.
3.0 1. Remove -10 bin ( tCD=10ns)
Draft Date
March. 25. 1999
May. 27. 1999
June. 22. 1999
Remark
Preliminary
Preliminary
Preliminary
Sep. 04. 1999
Preliminary
Nov. 19. 1999
Preliminary
Dec. 08. 1999
Nov. 23. 2000
Feb. 23. 2001
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - February 2001
Rev 3.0
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K7M163625M Datasheet
Recommendation K7M163625M Datasheet
Part K7M163625M
Description (K7M161825M / K7M163625M) 512Kx36 & 1Mx18 Flow-Through NtRAM
Feature K7M163625M; ( DataSheet : www.DataSheet4U.com ) K7M163625M K7M161825M Document Title 512Kx36 & 1Mx18 Flow-Thro.
Manufacture Samsung semiconductor
Datasheet
Download K7M163625M Datasheet




Samsung semiconductor K7M163625M
K7M163625M
K7M161825M
512Kx36 & 1Mx18 Flow-Through NtRAMTM
512Kx36 & 1Mx18-Bit Flow Through NtRAMTM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
FAST ACCESS TIMES
Parameter
Symbol -75 -85 -90 Unit
Cycle Time
tCYC 8.5 10 10 ns
Clock Access Time
tCD 7.5 8.5 9.0 ns
Output Enable Access Time tOE 4.0 4.0 4.0 ns
GENERAL DESCRIPTION
The K7M163625M and K7M161825M are 18,874,368-bits Syn-
chronous Static SRAMs.
The N tRAM TM, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M163625M and K7M161825M are implemented with
SAMSUNG s high performance CMOS technology and is avail-
able in 100pin TQFP and 119BGA packages. Multiple power
and ground pins minimize ground bounce.
LOGIC BLOCK DIAGRAM
A [0:18]or
A [0:19]
LBO
ADDRESS
A0~A1
REGISTER A2 ~A18 or A2 ~A19
BURST
ADDRESS
COUNTER
A0~A1
512Kx36 , 1Mx18
MEMORY
ARRAY
CLK
CKE
K
CS1
CS2
CS2
ADV
WE
BWx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8
DQPa ~ DQPd
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
DATA-IN
K REGISTER
36 or 18
BUFFER
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.
- 2 - February 2001
Rev 3.0



Samsung semiconductor K7M163625M
K7M163625M
K7M161825M
PIN CONFIGURATION(TOP VIEW)
512Kx36 & 1Mx18 Flow-Through NtRAMTM
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
Vss
V DD
V DD
VSS
DQd 0
DQd 1
VDDQ
VSSQ
DQd 2
DQd 3
DQd 4
DQd 5
VSSQ
VDDQ
DQd 6
DQd 7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M163625M(512Kx36)
80 DQPb
79 DQb7
78 DQb6
77 VDDQ
76 VSSQ
75 DQb5
74 DQb4
73 DQb3
72 DQb2
71 VSSQ
70 VDDQ
69 DQb1
68 DQb0
67 VSS
66 VSS
65 VDD
64 ZZ
63 DQa7
62 DQa6
61 VDDQ
60 VSSQ
59 DQa5
58 DQa4
57 DQa3
56 DQa2
55 VSSQ
54 VDDQ
53 DQa1
52 DQa0
51 DQPa
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A18
ADV
WE
CLK
CKE
CS1
CS2
CS2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,84,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
VDD
VSS
N.C.
DQa0~a 7
DQb0~b 7
DQc0~c7
DQd0~d 7
DQPa~Pd
VDDQ
VSSQ
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
No Connect
38,39,42,43
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 3 - February 2001
Rev 3.0







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