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Processor Core. MIPS324KM Datasheet

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Processor Core. MIPS324KM Datasheet






MIPS324KM Core. Datasheet pdf. Equivalent




MIPS324KM Core. Datasheet pdf. Equivalent





Part

MIPS324KM

Description

Processor Core

Manufacture

MIPS Technologies

Datasheet
Download MIPS324KM Datasheet


MIPS Technologies MIPS324KM

MIPS324KM; ( DataSheet : www.DataSheet4U.com ) MIP S32 4Km™ Processor Core Datasheet Ma rch 6, 2002 The MIPS32™ 4Km™ core from MIPS® Technologies is a member of the MIPS32 4K™ processor core family . It is a high-performance, low-power, 32-bit MIPS RISC core designed for cust om system-on-silicon applications. The core is designed for semiconductor manu facturing companies, ASIC d.


MIPS Technologies MIPS324KM

evelopers, and system OEMs who want to r apidly integrate their own custom logic and peripherals with a high-performanc e RISC processor. It is highly portable across processes, and can be easily in tegrated into full system-on-silicon de signs, allowing developers to focus the ir attention on end-user products. The 4Km core is ideally positioned to suppo rt new products fo.


MIPS Technologies MIPS324KM

r emerging segments of the digital consu mer, network, systems, and information management markets, enabling new tailor ed solutions for embedded applications. The 4Km core implements the MIPS32 Arc hitecture and contains all MIPS II™ i nstructions; special multiply-accumulat e (MAC), conditional move, prefetch, wa it, and leading zero/one detect instruc tions; and the 32-bi.



Part

MIPS324KM

Description

Processor Core

Manufacture

MIPS Technologies

Datasheet
Download MIPS324KM Datasheet




 MIPS324KM
( DataSheet : www.DataSheet4U.com )
MIPS32 4Km™ Processor Core Datasheet
March 6, 2002
The MIPS32™ 4Km™ core from MIPS® Technologies is a member of the MIPS32 4K™ processor core family. It is a
high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is
designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate
their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and
can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user
products. The 4Km core is ideally positioned to support new products for emerging segments of the digital consumer,
network, systems, and information management markets, enabling new tailored solutions for embedded applications.
The 4Km core implements the MIPS32 Architecture and contains all MIPS II™ instructions; special multiply-accumulate
(MAC), conditional move, prefetch, wait, and leading zero/one detect instructions; and the 32-bit privileged resource
architecture. The Memory Management Unit consists of a simple, fixed Block Address Translation (BAT) mechanism for
applications that do not require the full capabilities of a Translation Lookaside Buffer based MMU.
The synthesizable 4Km core implements single cycle MAC instructions, which enable DSP algorithms to be performed
efficiently. The Multiply/Divide Unit (MDU) allows 32-bit x 16-bit MAC instructions to be issued every cycle. A 32-bit x
32-bit MAC instruction can be issued every 2 cycles.
Instruction and data caches are fully configurable from 0 - 16 Kbytes in size. In addition, each cache can be organized as
direct-mapped or 2-way, 3-way, or 4-way set associative. Load and fetch cache misses only block until the critical word
becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches
are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated.
An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data
virtual address breakpoints.
Figure 1 shows a block diagram of the 4Km core. The core is divided into required and optional blocks as shown.
Mul/Div Unit
Processor Core
Instruction
Cache
EJTAG
Execution
Core
MMU
Cache
Control
System
Coprocessor
BAT
Data
Cache
Power
Mgmt.
Fixed/Required
Optional
Figure 1 4Km Core Block Diagram
MIPS32 4Km™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.
www.DataSheet4U.com





 MIPS324KM
Features
• 32-bit Address and Data Paths
• MIPS32-Compatible Instruction Set
– All MIPS II Instructions
– Multiply-Accumulate and Multiply-Subtract
Instructions (MADD, MADDU, MSUB, MSUBU)
– Targeted Multiply Instruction (MUL)
– Zero/One Detect Instructions (CLZ, CLO)
– Wait Instruction (WAIT)
– Conditional Move Instructions (MOVZ, MOVN)
– Prefetch Instruction (PREF)
• Programmable Cache Sizes
– Individually configurable instruction and data caches
– Sizes from 0 - 16KB
– Direct Mapped, 2-, 3-, or 4-Way Set Associative
– Loads block only until critical word is available
– Write-through, no write-allocate
– 16-byte cache line size, word sectored
– Virtually indexed, physically tagged
– Cache line locking support
– Non-blocking prefetches
• Scratchpad RAM Support
– Can optionally replace 1 way of the I- and/or D-cache
with a fast scratchpad RAM
– 20 index address bits allow access of arrays up to 1MB
– Memory-mapped registers attached to the scratchpad
port can be used as a coprocessor interface
• R4000®-style Privileged Resource Architecture
– Count/Compare registers for real-time timer interrupts
– I and D watch registers for SW breakpoints
– Separate interrupt exception vector
• Memory Management Unit
– Simple Block Address Translation (BAT) mechanism
• Simple Bus Interface Unit (BIU)
– All I/Os fully registered
– Separate unidirectional 32-bit address and data buses
– Two 16-byte collapsing write buffers
• Multiply/Divide Unit
– Maximum issue rate of one 32x16 multiply per clock
– Maximum issue rate of one 32x32 multiply every other
clock
– Early-in iterative divide. Minimum 11 and maximum 34
clock latency (dividend (rs) sign extension-dependent)
• Power Control
– Minimum frequency: 0 MHz
– Power-down mode (triggered by WAIT instruction)
– Support for software-controlled clock divider
• EJTAG Debug Support with single stepping, virtual
instruction and data address breakpoints
Architecture Overview
The 4Km core contains both required and optional blocks.
Required blocks are the lightly shaded areas of the block
diagram in Figure 1 and must be implemented to remain
MIPS-compliant. Optional blocks can be added to the 4Km
core based on the needs of the implementation.
The required blocks are as follows:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Memory Management Unit (MMU)
• Block Address Translation (BAT)
• Cache Controllers
• Bus Interface Unit (BIU)
• Power Management
Optional blocks include:
• Instruction Cache
• Data Cache
• Scratchpad RAM
• Enhanced JTAG (EJTAG) Controller
The section entitled "4Km Core Required Logic Blocks"
on page 3 discusses the required blocks. The section
entitled "4Km Core Optional Logic Blocks" on page 10
discusses the optional blocks.
Pipeline Flow
The 4Km core implements a 5-stage pipeline with
performance similar to the R3000® pipeline. The pipeline
allows the processor to achieve high frequency while
minimizing device complexity, reducing both cost and
power consumption.
The 4Km core pipeline consists of five stages:
• Instruction (I Stage)
• Execution (E Stage)
• Memory (M Stage)
• Align (A Stage)
2 MIPS32 4Km™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.





 MIPS324KM
• Writeback (W stage)
The 4Km core implements a bypass mechanism that allows
the result of an operation to be forwarded directly to the
instruction that needs it without having to write the result
to the register and then read it back.
Figure 2 shows a timing diagram of the 4Km core pipeline.
I
I-Cache
EM
Bypass
Bypass
RegRd ALU Op
I Dec D-AC D-Cache
A
Align
I-A1 I-A2
Bypass
Mul-16x16, 32x16
Bypass
Mul-32x32
Div
Acc
Acc
Acc
W
RegW
RegW
RegW
RegW
Figure 2 4Km Core Pipeline
I Stage: Instruction Fetch
During the Instruction fetch stage:
• An instruction is fetched from instruction cache.
E Stage: Execution
During the Execution stage:
• Operands are fetched from register file.
• The arithmetic logic unit (ALU) begins the arithmetic
or logical operation for register-to-register instructions.
• The ALU calculates the data virtual address for load
and store instructions.
• The ALU determines whether the branch condition is
true and calculates the virtual branch target address for
branch instructions.
• Instruction logic selects an instruction address.
• All multiply and divide operations begin in this stage.
M Stage: Memory Fetch
During the memory fetch stage:
• The arithmetic ALU operation completes.
• The data cache fetch and the data virtual-to-physical
address translation are performed for load and store
instructions.
• Data cache look-up is performed and a hit/miss
determination is made.
• A 16x16 or 32x16 multiply calculation completes.
• A 32x32 multiply operation stalls for one clock in the
M stage.
• A divide operation stalls for a maximum of 34 clocks
in the M stage. Early-in sign extension detection on the
dividend will skip 7, 15, or 23 stall clocks.
A Stage: Align
During the Align stage:
• A separate aligner aligns load data to its word
boundary.
• A 16x16 or 32x16 multiply operation performs the
carry-propagate-add. The actual register writeback is
performed in the W stage.
• A MUL operation makes the result available for
writeback. The actual register writeback is performed
in the W stage.
W Stage: Writeback
• For register-to-register or load instructions, the
instruction result is written back to the register file
during the W stage.
4Km Core Required Logic Blocks
The 4Km core consists of the following required logic
blocks as shown in Figure 1. These logic blocks are defined
in the following subsections:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Memory Management Unit (MMU)
• Block Address Translation (BAT)
• Cache Controller
• Bus Interface Control (BIU)
• Power Management
MIPS32 4Km™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.
3



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