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bits DDR400. EDD2508AKTA-5 Datasheet

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bits DDR400. EDD2508AKTA-5 Datasheet







EDD2508AKTA-5 DDR400. Datasheet pdf. Equivalent




EDD2508AKTA-5 DDR400. Datasheet pdf. Equivalent





Part

EDD2508AKTA-5

Description

256M bits DDR SDRAM (32M words x 8 bits DDR400)

Manufacture

Elpida Memory

Datasheet
Download EDD2508AKTA-5 Datasheet


Elpida Memory EDD2508AKTA-5

EDD2508AKTA-5; ( DataSheet : www.DataSheet4U.com ) PRE LIMINARY DATA SHEET 256M bits DDR SDRA M EDD2508AKTA-5 (32M words × 8 bits, D DR400) Description The EDD2508AKTA-5 is a 256M bits DDR SDRAM organized as 8,3 88,608 words × 8 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is reali zed by the 2 bits pre.


Elpida Memory EDD2508AKTA-5

fetch-pipelined architecture. Data strob e (DQS) both for read and write are ava ilable for high speed and reliable data bus design. By setting extended mode r egister, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 66-pin plastic TSOP (II) . Pin Configurations /xxx indicates ac tive low signal. 66-pin Plastic TSOP(II ) VDD DQ0 VDDQ NC .


Elpida Memory EDD2508AKTA-5

DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC V DDQ NC NC VDD NC NC /WE /CAS /RAS /CS N C BA0 BA1 A10(AP) A0 A1 A2 A3 VDD Feat ures • Power supply: VDDQ = 2.6V ± 0 .1V : VDD = 2.6V ± 0.1V • Data rate: 400Mbps (max.) • Double Data Rate ar chitecture; two data transfers per cloc k cycle • Bi-directional, data strobe (DQS) is transmitted /received with da ta, to be used in capturing .



Part

EDD2508AKTA-5

Description

256M bits DDR SDRAM (32M words x 8 bits DDR400)

Manufacture

Elpida Memory

Datasheet
Download EDD2508AKTA-5 Datasheet




 EDD2508AKTA-5
( DataSheet : www.DataSheet4U.com )
PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AKTA-5 (32M words × 8 bits, DDR400)
Description
The EDD2508AKTA-5 is a 256M bits DDR SDRAM
organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in 66-pin plastic TSOP (II).
Features
Power supply: VDDQ = 2.6V ± 0.1V
: VDD = 2.6V ± 0.1V
Data rate: 400Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 3
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS
65 DQ7
64 VSSQ
63 NC
62 DQ6
61 VDDQ
60 NC
59 DQ5
58 VSSQ
57 NC
56 DQ4
55 VDDQ
54 NC
53 NC
52 VSSQ
51 DQS
50 NC
49 VREF
48 VSS
47 DM
46 /CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0349E60 (Ver. 6.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005
www.DataSheet4U.com





 EDD2508AKTA-5
EDD2508AKTA-5
Ordering Information
Part number
EDD2508AKTA-5B
EDD2508AKTA-5C
Mask
version
K
Organization
(words × bits)
32M × 8
Internal
banks
4
Data rate
Mbps (max.)
400
JEDEC speed bin
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR400C (3-4-4)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 25 08 A K TA - 5B
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Organization
8: x8
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
TA: TSOP (II)
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
Preliminary Data Sheet E0349E60 (Ver. 6.0)
2





 EDD2508AKTA-5
EDD2508AKTA-5
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................39
Package Drawing ........................................................................................................................................45
Recommended Soldering Conditions..........................................................................................................46
Preliminary Data Sheet E0349E60 (Ver. 6.0)
3



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