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Output Expander. MB88307 Datasheet

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Output Expander. MB88307 Datasheet






MB88307 Expander. Datasheet pdf. Equivalent




MB88307 Expander. Datasheet pdf. Equivalent





Part

MB88307

Description

(MB88306 - MB88309) CMOS Output Expander

Manufacture

Fujitsu

Datasheet
Download MB88307 Datasheet


Fujitsu MB88307

MB88307; ( DataSheet : www.DataSheet4U.com ) w w w .D S a at U 4 t e he m o .c .


Fujitsu MB88307

.


Fujitsu MB88307

.



Part

MB88307

Description

(MB88306 - MB88309) CMOS Output Expander

Manufacture

Fujitsu

Datasheet
Download MB88307 Datasheet




 MB88307
• MB88306 MB88307 MB88308
MB88309
CMOS Output Expander
FUJITSU
October 19B6
DESCRIPTION
Each of the four expanders provides a serial 1/0 port and an B-bit paral-
lel output port. Data is serially loaded via the input port, converted to an
B-bit parallel format, and latched. The latched data is then transferred to
the parallel output port for distribution. The B-bit output port can directly
drive a Light Emitting Diode (LED) display; the LED display can be ex-
panded in byte-size increments to make any desired configuration. In
terms of output drive and shift clock triggers, each expander is unique-
see description that follows.
Expander
MBBB306
MBBB307
MBBB30B
MBBB309
Output
CMOS 3-State
NMOS Dilen Drain
CMOS 3-State
NMOS Open Drain
Shift Clock Trigger
Rising Edge
Rising Edge
Falling Edge
Falling Edge
MBBB306171B/9 are fabricated by a silicon-gate CMOS process and are
packaged in a standard 16-pin plastic DIP or SOP. All four expanders
operate with a single + SV power source and a 2 MHz shift clock over
an ambient temperature range of -40'C to + BS'C.
FEATURES
• B-bit parallel output
• Serial input/output
• Expandable in B-bit increments
• LED direct drive capability: 15 rnA max at 1.2V
• Two output port types:
-CMOS 3-state output
(MBBB306/B)
-NMOS open-drain output (MBBB307/9)
• Two shift clock polarities:
-Rising-edge-triggering (MBBB306/7)
-Falling-edge-triggering (MBBB30B/9)
• Simple interface to Fujitsu 4-bit microcomputers
• TTL compatible outputs
• Single + SV power supply
• Silicon-gate CMOS process
• Two package options:
-16-pin plastic DIP (Suffix -P)
-16-pin plastic SOP (Suffix -PF)
Copyright @ 1986 by Fujitsu limited and Fujitsu Subsidiaries worldwide.
This document contains information considered proprietary by Fujitsu limited, Tokyo. Japan and
its subsidiaries. No part of this document may be copied or reproduced in any form or by any
means, or transferred to any third party without the prior written consent of Fujitsu Limited.
2-192
8306-1
Plastic DIP (Suffix -P)
DIP-16P-M02
8306-2
Plastic SOP (Suffix -PF)
FPT-16P-M02
Pin Assignments
so
LOAD
00
01
02
03
SC(iC)
V. .
Vee
IiESEf
Sl
07
os
05
04
l5E
8306-3
Note;
SC is applicable to MB88306 and MB88307
SC is applicable to MB88308 and MB88309
This device contains circuitry to protect the in-
puts against damage due to rn9h static voltages
or electric fields. However. it is advised that nor·
mal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high impedance cirCuit.
838306





 MB88307
MB8830e
MB88307
MB88308
MB8830e
Figure t. Block Diagram
DE - - - - I
Vee
Vss_
SI
PROCESSOR
INTERFACE
07 06 05
03 02 01 00
Figure 2. System Intertace
+5V
T
Vee
.
M. . . . . .
MIIII8307
Ma_
Ma_
07
06
05
04 MRALLEL
OATAOUTPUT
03
02
01
00
SO SERIAL
DATA OUTPUT
8306-4
EXPANSION
PORT
FUJITSU
Vss
1
Note:
SC for M88830617; ~ for MB88308/9
2-193
8306-5





 MB88307
MB88308
MB88307
MB88308
MB88309
PIN DESCRIPTION
Figures 1 and 2 show the pin assignment and logic symbol of the MB883061718/9. Table 1 shows the pin description. The
MB88306/7/8/9 have two interfaces: one is the processor interface; SI, SC (SC), RESET, LOAD, and dE inputs; the other is the
expansion output port; 07-00, and SO outputs.
Table 1: Pin Description
Name &Function
Processor Interface
SI 14
SC 4
(SC)
RESET
LOAD
15
2
bE 9
Expansion Port
07-00
13-10,
6-3
SO 1
+ 5V dc power supply pin.
Power supply ground pin.
I Serial data input to the internal shift register: A data bit on the SI pin is shifted into the
MSB of the shift register at the rising edge (MB8830617) of the shift clock SC or the
falling edge (MB88308/9) of the shift clock for SC. The data bits are transferred from
the processor or from the SO pin of the cascaded devices.
I Shift clock input for the internal shift register: The rising edge of SC (MB8830617) or
falling edge of SC (MB88308/9) shifts a data bit on the SI pin into the MSB of the shift
register, each bit of the shift register is shifted right, and the LSB of the shift register
appears directly on the SO pin. A high level and low level and the falling edge
(MB8830617) or the rising edge (MB88308/9) keep contents of the shift register. This
is a hysteresis input.
I Preset input for the internal data latch: A low level on the RESET pin initializes the data
latch in high state, and also inhibits the LOAD input. This is a hysteresis input. The
RESET input does not affect the shift register and the output drain.
I Load enable input for the internal data latch: A low level on the LOAD pin transfers 8-bit
parallel data of the shift register into the data latch. A high level inhibits data
transmission from the shift register to the data latch, to hold contents of the data latch.
This input is automatically inhibited when the RESET input is activated (low). This is a
hysteresis input.
I Output enable input of the output driver: A low level on the OE pin outputs 8-bit data of
the data latch on the data output pins 07-00. A high level places the 07-00 pins in
high impedance state. The bE pin does not control the SO output.
0 Parallel data output: This is an 8-bit 3-state data output port. This port outputs 8-bit
data in the data latch when the bE pin is activated (low), and is placed in high
impedance state when the OE pin is inactive (high). This port is CMOS 3-state output
(MB88306/8) or NMOS open-drain output (MB88307/9). Both output drivers can
directly drive LEDs. The MSB and LSB of the shift register are output onto the 07 and
00 pins, respectively. These pins are TTL compatible.
0 Serial data output of the internal shift register: The LSB of the shift register appears
directly onto the SO pin with some delay time because the SO output has no output
latch. This pin is used to cascade devices to expand the data output port in 8-bit units.
This pin is TTL compatible but is not 3-state output controlled by the OE pin.
FUJITSU
2-194



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