ICD2053B Datasheet PDF


Part Number

ICD2053B

Description

Programmable Clock Generator

Manufacture

Cypress

Total Page 8 Pages
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Download ICD2053B Datasheet PDF


Features Datasheet pdf ( DataSheet : www.DataSheet4U.com ) ICD 2053B Programmable Clock Generator Fea tures • Clock outputs ranging from 39 1 kHz to 100 MHz (TTL levels) or 90 MHz (CMOS levels) • 2-wire serial interf ace facilitates programmable output fre quency • Phase-Locked Loop oscillator input derived from external reference clock (1 MHz to 25 MHz) or External Cry stal (2 MHz to 24 MHz) • Three-State output control disables output for test purposes • Sophisticated internal lo op filter requires no external componen ts or manufacturing tweaks as commonly required with external filters • Low power consumption makes device ideal fo r powerand space-critical applications • 8-pin 150-mil packaging achieves minimum footp.
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ICD2053B Datasheet
( DataSheet : www.DataSheet4U.com )
ICD2053B
Programmable Clock Generator
Features
• Clock outputs ranging from 391 kHz to 100 MHz (TTL
levels) or 90 MHz (CMOS levels)
• 2-wire serial interface facilitates programmable output
frequency
• Phase-Locked Loop oscillator input derived from exter-
nal reference clock (1 MHz to 25 MHz) or External Crys-
tal (2 MHz to 24 MHz)
• Three-State output control disables output for test pur-
poses
• Sophisticated internal loop filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
• Low power consumption makes device ideal for power-
and space-critical applications
• 8-pin 150-mil packaging achieves minimum footprint
for space-critical applications
• 5V operation
• High-speed CMOS technology
Functional Description
The ICD2053B Programmable Clock Generator offers a fully
user-programmable phase-locked loop in a single 8-pin pack-
age. The output may be changed “on the fly” to any desired
frequency value between 391 kHz and 100 MHz (90 MHz at
CMOS levels). The ICD2053B is ideally suited for any design
in which package size, power, and/or frequency programma-
bility are important design issues.
The ability to dynamically change the output frequency adds a
whole new degree of freedom for the designer. Some exam-
ples of the uses for this device include: laptop computers, in
which slowing the speed of operation can mean less power
consumption; graphics board dot clocks to allow dynamic syn-
chronization of different brands of monitors or display formats;
on-board test strategies where the ability to skew a system’s
desired frequency (e.g., ±10%) allows worst-case evaluation.
Logic Block Diagram
Pin Configuration
XTALIN
XTALOUT
SCLK
DATA
MUXREF/OE
Top View
XTALOUT
1
8 XTALIN
SCLK
2
7 MUXREF/OE
GND
3
6 VDD
DATA
4
5 CLKOUT
.comREFERENCE
et4UOSCILLATOR
÷Q f(REF)
f OUT
PLL
÷2P f OUT
MUX
÷2N
She7 7
5
3
www.DataCONTROL LOGIC
2053b-1
CLKOUT
VDD GND
2053b-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 1994 - Revised October 1995




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