DatasheetsPDF.com

TV Encoder. CH7203 Datasheet

DatasheetsPDF.com

TV Encoder. CH7203 Datasheet
















CH7203 Encoder. Datasheet pdf. Equivalent













Part

CH7203

Description

MPEG to TV Encoder



Feature


www.DataSheet4U.com CH7203 CHRONTEL MP EG to TV Encoder with 16-bit Input Feat ures • • • • • • • • • • • • • Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60 16-bit Y CrCb (4:2:2) input format Simultaneous composite/S-video outputs Triple 9-bit video DACs 27 MHz DAC operating frequen cy eliminates the need for 1/sinc(x) co rrection filter Low-jitter phase-locked loop c.
Manufacture

ETC

Datasheet
Download CH7203 Datasheet


ETC CH7203

CH7203; ircuitry operates using a low-cost 14.31 818 MHz crystal 40.5 or 33.9 MHz video decoder clock output 16.934 or 11.289 M Hz audio decoder clock output 13.5 MHz and 27 MHz video pixel clock outputs Op timized luminance and chrominance inter nal filters for NTSC and PAL HSYNC* and VSYNC* outputs for master mode operati on Sleep mode CMOS technology in 44-pin PLCC 5V single-su.


ETC CH7203

pply operation Description The CH7203 v ideo encoder integrates a dual PLL cloc k generator and a digital NTSC/PAL vide o encoder. By generating all essential clock signals for MPEG playback, and co nverting digital video inputs to either NTSC or PAL video signals, the CH7203 is an essential component of any low-co st solution for video-CD playback machi nes. The CH7203 du.


ETC CH7203

al PLL clock synthesizer generates all c locks and timing signals from a 14.3181 8 MHz reference crystal (see applicatio n note 19 “Tuning Clock Outputs” fo r selection and tuning of the 14.31818 MHz crystal). The CH7203 generates a 40 .5 or 33.9 MHz video decoder clock, 13. 5 MHz and 27 MHz video pixel clocks, an d a 16.934 or 11.289 MHz audio decoder clock. Timing signals .





Part

CH7203

Description

MPEG to TV Encoder



Feature


www.DataSheet4U.com CH7203 CHRONTEL MP EG to TV Encoder with 16-bit Input Feat ures • • • • • • • • • • • • • Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60 16-bit Y CrCb (4:2:2) input format Simultaneous composite/S-video outputs Triple 9-bit video DACs 27 MHz DAC operating frequen cy eliminates the need for 1/sinc(x) co rrection filter Low-jitter phase-locked loop c.
Manufacture

ETC

Datasheet
Download CH7203 Datasheet




 CH7203
www.DataSheet4U.com
CHRONTEL
CH7203
MPEG to TV Encoder with 16-bit Input
Features
• Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60
• 16-bit YCrCb (4:2:2) input format
• Simultaneous composite/S-video outputs
• Triple 9-bit video DACs
• 27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
• Low-jitter phase-locked loop circuitry operates
using a low-cost 14.31818 MHz crystal
• 40.5 or 33.9 MHz video decoder clock output
• 16.934 or 11.289 MHz audio decoder clock output
• 13.5 MHz and 27 MHz video pixel clock outputs
• Optimized luminance and chrominance internal
filters for NTSC and PAL
• HSYNC* and VSYNC* outputs for
master mode operation
• Sleep mode
• CMOS technology in 44-pin PLCC
• 5V single-supply operation
Description
The CH7203 video encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTSC or PAL video signals, the CH7203 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7203 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7203 generates a 40.5 or 33.9
MHz video decoder clock, 13.5 MHz and 27 MHz
video pixel clocks, and a 16.934 or 11.289 MHz audio
decoder clock. Timing signals from the PLLs are used
to generate the horizontal and vertical sync signals
which enable operating the CH7203 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
MOD 0
MOD 1
FS
C RSEN*
CR S
VDD
AVDD
R SET
Y[7 :0],
C[7:0 ]
16
I NTE RFACE
H SYNC*
VSYNC*
S TAT E
M ACHI NE
BL AN KING
H ,V SYNC
GEN ERATO R
L INE AR
INTE RP OLATO R
Y
FILTER
M
U
X
U
FILTER
M
U
X
X
IR EF
9 DAC
Σ 9 DAC
Σ 9 DAC
PC LK
2XPC LK
DC LK
1/ 2
PLL1
V
FILTER
M
U
X
X
A CLK
PLL2
www.DataSheet4U.com
201-0000-031 Rev 2.0, 6/2/99
OSC
B LA NKIN G
COL O R-B URST
CO NT RO L
S IN + COSINE
GEN ER ATOR
XI XO/FIN
GN D
A GN D
Figure 1: Functional Block Diagram
Y
CVB S
C
1




 CH7203
www.DataSheet4U.com
CHRONTEL
CH7203
CRSEN*
FS
MOD1
CRS
C[7]
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
7
8
9
10
11
12
13
14
15
16
17
CHRONTEL
CH7203
39 PCLK
38 MOD0
37 VSYNC*
36 VDD
35 HSYNC*
34 GND
33 GND
32 Y
31 CVBS
30 C
29 AVDD
Figure 2: CH7203 Pinout Diagram
www.DataSheet4U.com
2
201-0000-031 Rev 2.0, 6/2/99




 CH7203
www.DataSheet4U.com
CHRONTEL
CH7203
Table 1. Pin Descriptions
Pin Type
1 Out
S ymbol
ACLK
2, 36, 42
Power
VDD
3 In XO/FIN
4 In
XI
5, 27
Power
AGND
6,29
7
Power
In
AVDD
CRSEN*
8
9
10
11 – 18
In
In
In
In
FS
MOD1
CRS
C[7:0]
Description
Audio Decoder Clock Output
16.934 MHz or 11.289 MHz clock output (selectable by FS) for
MPEG audio decoder operation. The output swing is 5V.
Digital Supply Voltage
These pins supply the 5V power to the digital section of the
CH7203.
Crystal Output or External FREF Input 1
A 14.31818 MHz (± 50 ppm) parallel resonance crystal may be
attached between XO/FIN and XI. An external CMOS compatible
clock can be connected to XO/FIN as an alternative.
Crystal Input 1
A 14.31818 MHz (± 50 ppm) parallel resonance crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.
Analog ground
These pins provide the ground reference for the analog section of
the CH7203. These pins MUST be connected to the system
ground to prevent latchup.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the
CH7203.
Cr Select Enable. Internally pulled-up.
CRSEN*=0, Cr, Cb data sequence is specified by the CRS pin.
CRSEN*=1, Cr, Cb data sequence is specified by the CH7203’s
internal default condition: Horizontal count = even, data is Cb;
data is Cr otherwise. State of CRS is ignored when CRSEN*=1.
See Figure 6 on page 7.
Frequency Select. Internally pulled-up
FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz
Mode bit 1 - Internally pulled-up
This input works in conjunction with the MOD0 input to select
NTSC, PAL, or Sleep mode functions. Refer to Table 3, “Video
Encoder Modes,” on page 6 for details.
Cr Select.
When CRSEN*=0, CRS specifies the CrCb data sequence. CRS
is an alternating signal. CRS=1 indicates that C[7:0] carry the Cr
data. C[7:0] carry the Cb data otherwise. See Figure 7 on page 8.
Video Input
These pins accept the “CrCb” data of the YCrCb (4:2:2) digital
video format. The Cb & Cr data appear alternately. The sequence
of the Cb, Cr data is either predefined by the internal horizontal
counter (even = Cb, odd = Cr) or as specified by pin CRS (data is
Cr for CRS=1 and Cb otherwise. For more details, please refer to
the timing diagram shown in Figure 6 on page 7.
Cb & Cr have a nominal range of 16–240, with 128 equal to zero.
Note: 1. Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capac-
wwitwor s.DhoualdtabeSohbteaineetd4frUom.cthoe mcrystal manufacturer. For further information, request a copy of Application Note AN-19, “Tuning Clock
Outputs.
201-0000-031 Rev 2.0, 6/2/99
3




Recommended third-party CH7203 Datasheet







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)