TV Encoder. CH7203 Datasheet

CH7203 Encoder. Datasheet pdf. Equivalent

Part CH7203
Description MPEG to TV Encoder
Feature www.DataSheet4U.com CH7203 CHRONTEL MPEG to TV Encoder with 16-bit Input Features • • • • • • • • .
Manufacture ETC
Total Page 15 Pages
Datasheet
Download CH7203 Datasheet



CH7203
www.DataSheet4U.com
CHRONTEL
CH7203
MPEG to TV Encoder with 16-bit Input
Features
• Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60
• 16-bit YCrCb (4:2:2) input format
• Simultaneous composite/S-video outputs
• Triple 9-bit video DACs
• 27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
• Low-jitter phase-locked loop circuitry operates
using a low-cost 14.31818 MHz crystal
• 40.5 or 33.9 MHz video decoder clock output
• 16.934 or 11.289 MHz audio decoder clock output
• 13.5 MHz and 27 MHz video pixel clock outputs
• Optimized luminance and chrominance internal
filters for NTSC and PAL
• HSYNC* and VSYNC* outputs for
master mode operation
• Sleep mode
• CMOS technology in 44-pin PLCC
• 5V single-supply operation
Description
The CH7203 video encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTSC or PAL video signals, the CH7203 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7203 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7203 generates a 40.5 or 33.9
MHz video decoder clock, 13.5 MHz and 27 MHz
video pixel clocks, and a 16.934 or 11.289 MHz audio
decoder clock. Timing signals from the PLLs are used
to generate the horizontal and vertical sync signals
which enable operating the CH7203 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
MOD 0
MOD 1
FS
C RSEN*
CR S
VDD
AVDD
R SET
Y[7 :0],
C[7:0 ]
16
I NTE RFACE
H SYNC*
VSYNC*
S TAT E
M ACHI NE
BL AN KING
H ,V SYNC
GEN ERATO R
L INE AR
INTE RP OLATO R
Y
FILTER
M
U
X
U
FILTER
M
U
X
X
IR EF
9 DAC
Σ 9 DAC
Σ 9 DAC
PC LK
2XPC LK
DC LK
1/ 2
PLL1
V
FILTER
M
U
X
X
A CLK
PLL2
www.DataSheet4U.com
201-0000-031 Rev 2.0, 6/2/99
OSC
B LA NKIN G
COL O R-B URST
CO NT RO L
S IN + COSINE
GEN ER ATOR
XI XO/FIN
GN D
A GN D
Figure 1: Functional Block Diagram
Y
CVB S
C
1



CH7203
www.DataSheet4U.com
CHRONTEL
CH7203
CRSEN*
FS
MOD1
CRS
C[7]
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
7
8
9
10
11
12
13
14
15
16
17
CHRONTEL
CH7203
39 PCLK
38 MOD0
37 VSYNC*
36 VDD
35 HSYNC*
34 GND
33 GND
32 Y
31 CVBS
30 C
29 AVDD
Figure 2: CH7203 Pinout Diagram
www.DataSheet4U.com
2
201-0000-031 Rev 2.0, 6/2/99





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)