MM74C32. 74C32 Datasheet

74C32 MM74C32. Datasheet pdf. Equivalent

Part 74C32
Description MM74C32
Feature MM74C32 Quad 2-Input OR Gate October 1987 Revised May 2002 MM74C32 Quad 2-Input OR Gate General D.
Manufacture Fairchild
Datasheet
Download 74C32 Datasheet



74C32
October 1987
Revised May 2002
MM74C32
Quad 2-Input OR Gate
General Description
The MM74C32 employs complementary MOS (CMOS)
transistors to achieve low power and high noise margin,
these gates provide the basic functions used in the imple-
mentation of digital integrated circuit systems. The N- and
P-channel enhancement mode transistors provide a sym-
metrical circuit with output swings essentially equal to the
supply voltage. This results in high noise immunity over a
wide supply voltage range. No DC power other than that
caused by leakage current is consumed during static con-
ditions. All inputs are protected against static discharge
damage.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45V VCC (typ.)
s Low power TTL compatibility: fan out of 2 driving 74L
Ordering Code:
Order Number Package Number
Package Description
MM74C32M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74C32N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
© 2002 Fairchild Semiconductor Corporation DS005881
www.fairchildsemi.com



74C32
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VCC Range
0.3V to VCC + 0.3V
55°C to +125°C
65°C to +150°C
700 mW
500 mW
3.0V to 15V
Absolute Maximum VCC
Lead Temperature
18V
(Soldering, 10 seconds)
260°C
Note 1: Absolute Maximum Ratingsare those values beyond which the
safety of the device cannot be guaranteed. Except for Operating Tempera-
ture Rangethey are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
VIN(1)
Logical 1Input Voltage
VIN(0)
Logical 0Input Voltage
VOUT(1)
Logical 1Output Voltage
VOUT(0)
Logical 0Output Voltage
IIN(1)
Logical 1Input Current
IIN(0)
Logical 0Input Current
ICC Supply Current
CMOS/LPTTL INTERFACE
VCC = 5.0V
VCC = 10V
VCC = 5.0V
VCC = 10V
VCC = 5.0V, IO = −10 µA
VCC = 10V, IO = −10 µA
VCC = 5.0V, IO = 10 µA
VCC = 10V, IO = 10 µA
VCC = 15V, VIN = 15V
VCC = 15V, VIN = 0V
VCC = 15V
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical 1Input Voltage
Logical 0Input Voltage
Logical 1Output Voltage
Logical 0Output Voltage
VCC = 4.75V
VCC = 4.75V
VCC = 4.75V, IO = −360 µA
VCC = 4.75V, IO = 360 µA
OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)
ISOURCE
Output Source Current
(P-Channel)
VCC = 5.0V, VOUT = 0V
ISOURCE
Output Source Current
(P-Channel)
VCC = 10V, VOUT = 0V
ISINK
Output Sink Current
(N-Channel)
VCC = 5.0V, VOUT = VCC
ISINK
Output Sink Current
(N-Channel)
VCC = 10V, VOUT = VCC
Min Typ
3.5
8.0
4.5
9.0
0.005
1.0 0.005
0.05
VCC 1.5
2.4
1.75
8.0
1.75
8.0
3.3
15
3.6
16
Max
1.5
2.0
0.5
1.0
1.0
15
0.8
0.4
Units
V
V
V
V
µA
µA
µA
V
V
V
V
mA
mA
mA
mA
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max
Units
tpd Propagation Delay Time to
VCC = 5.0V
Logical 1or 0
VCC = 10V
CIN Input Capacitance
Any Input (Note 3)
CPD
Power Dissipation Capacitance
Per Gate (Note 4)
80 150
35 70
5
15
ns
ns
pF
pF
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note
AN-90.
www.fairchildsemi.com
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