EP314 Datasheet PDF Download, Altera





(PDF) EP314 Datasheet Download

Part Number EP314
Description (EP312 / EP314) Classic FPLDs
Manufacture Altera
Total Page 18 Pages
PDF Download Download EP314 Datasheet PDF

Features: www.DataSheet4U.com ® EP312 & EP324 C lassic EPLDs Data Sheet April 1995, ve r. 1 Features s s s s s s s s s s s s s s High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP 324) – Combinatorial speeds as fast a s 25 ns – Counter frequencies of up t o 33.3 MHz – Pipelined data rates of up to 66 MHz Multiple 20-pin PAL and GA L replacement and integration Device er asure and reprogramming with advanced, nonvolatile EPROM configuration element s Programmable registers providing D, T , JK, and SR flipflops with individual Clear and Clock controls Dual feedback on all macrocells for implementing buri ed registers with bidirectional I/O Pro grammable-AND/allocatable-OR structure allowing up to 16 product terms per mac rocell DataShee Two product terms on al l macrocell control signals Programmabl e inputs (8 in EP312, 10 in EP324) conf igurable as DataSheet4U.com latches, re gisters, or flow-through input Availabl e in windowed ceramic and one-time-programmable (OTP) plastic packages.

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www.DataSheet4U.com
April 1995, ver. 1
®
EP312 & EP324
Classic EPLDs
Data Sheet
Features
General
Description
DataSheet4U.com
Altera Corporation
A-DS-312/324.01
DataSheet4 U .com
s High-performance EPLDs with 12 macrocells (EP312) or 24
macrocells (EP324)
– Combinatorial speeds as fast as 25 ns
– Counter frequencies of up to 33.3 MHz
– Pipelined data rates of up to 66 MHz
s Multiple 20-pin PAL and GAL replacement and integration
s Device erasure and reprogramming with advanced, nonvolatile
EPROM configuration elements
s Programmable registers providing D, T, JK, and SR flipflops with
individual Clear and Clock controls
s Dual feedback on all macrocells for implementing buried registers
with bidirectional I/O
s Programmable-AND/allocatable-OR structure allowing up to 16
product terms per macrocell
s Two product terms on all macrocell control signals
DataShee
s Programmable inputs (8 in EP312, 10 in EP324) configurable as
latches, rDegaitsateSrhs,eoert4flUow.c-othmrough input
s Available in windowed ceramic and one-time-programmable (OTP)
plastic packages with 24 to 44 pins:
– 24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)
– 40-pin CerDIP and PDIP
– 44-pin PLCC
s One global Clock pin; one global Input Latch Enable/Input
Clock/Input (ILE/ICLK/INPUT) pin
s Programmable “standby” option for low-power operation
s Programmable Security Bit for total protection of proprietary designs
s 100% generically testable to provide 100% programming yield
s Software design support with the Altera PLDshell Plus software and
a wide range of third-party tools; programming support through
third-party vendors
The CMOS EPROM EP312 and EP324 devices have a versatile macrocell
structure and I/O architecture, which allow them to implement high-
performance logic functions effectively. The EP312 and EP324 input and
macrocell features are a superset of features offered by PAL/GAL
devices. Therefore, EP312 and EP324 devices can be used as an alternative
to multiple PAL/GAL devices, SSI and MSI logic devices, or low-end gate
arrays.
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