68HC16 Module. 68HC16 Datasheet
19-1322; Rev 0; 12/97
_____________________________________________68HC16 Module Component List
C1, C2, C3
1µF ceramic capacitors
22µF, 25V radial-lead electrolytic
Reference designator, not used
40-pin right-angle male connector
2-circuit terminal block
Right-angle printed circuit board
mount, DB9 female socket
Reference designator, not used
10MΩ, 5% resistor
330kΩ, 5% resistor
10kΩ, 5% resistors
470Ω, 5% resistor
10kΩ SIP resistor
Momentary pushbutton switch
plastic quad flat pack)
27C256 EPROM containing
7805 regulator, TO-220 size
62256 (32K x 8) static RAM
74HCT245 bidirectional buffer
32.768kHz watch crystal
28-pin socket for U3
20-pin socket for U6
3" x 5" printed circuit board
Heatsink for U4, thermalloy # 6078
The 68HC16 module is an assembled and tested print-
ed-circuit board intended for use with Maxim’s high-
speed serial-interface evaluation kits (EV kits). The
module uses an inexpensive 8-bit implementation of
Motorola’s MC68HC16Z1 microcontroller (µC) to collect
data samples at high speed using the QSPI™ interface.
It requires an IBM-compatible personal computer and
an external DC power supply, typically 12V DC or as
specified in EV kit manual.
Maxim’s 68HC16 module is provided to allow customers
to evaluate selected Maxim products. It is not intended
to be used as a microprocessor development platform,
and such use is not supported by Maxim.
QSPI is a trademark of Motorola Corp.
Power Input Connector J2
The 68HC16 module draws its power from a user-sup-
plied power source connected to terminal block J2. Be
sure to note the positive and negative markings on the
board. A three-terminal 5V regulator allows input voltages
between 8V and an absolute maximum of 20V. The
68HC16 module typically requires 200mA of input current.
U1 is Motorola’s 68HC16Z1 µC. Contact Motorola for µC
information, development, and support. Maxim EV kits use
the high-speed queued serial peripheral interface (QSPI)
and the internal chip-select generation.
A MAX707 on the module monitors the 5V logic supply,
generates the power-on reset, and produces a reset
pulse whenever the reset button is pressed.
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The 68HC16 uses a phase-locked loop (PLL) to set its
bus speed. Crystal Y1 is a 32.768kHz frequency refer-
ence. The internal oscillator runs 256 times faster than the
external crystal. When the 68HC16 is reset, it waits for the
PLL to lock before it executes any software. After the PLL
locks onto the reference frequency, the software doubles
the clock speed by writing to the clock synthesizer con-
trol register, selecting a bus speed of 16.78MHz.
U5, the user RAM area, is a 32kbyte CMOS static RAM.
The 74HCT245 octal buffer lets the 68HC16 module
access an 8-bit port on the 40-pin interface connector.
This memory-mapped port consists of separate read
and write strobes, four chip selects, four address LSBs,
and eight data bits.
Table 1. Serial Communications Port J3
Handshake; hard-wired to DTR and DSR
RS-232-compatible data output from
RS-232-compatible data input to
Handshake; hard-wired to DCD and DSR
Signal ground connection
Handshake; hard-wired to DCD and DTR
Handshake; hard-wired to CTS
Handshake; hard-wired to RTS
J3 is an RS-232 serial port, designed to be compatible Table 2. 40-Pin Data-Connector Signals
with the IBM PC 9-pin serial port. Use a straight-
through DB9 male-to-female cable to connect J3 to this
port. If the only available serial port has a 25-pin con-
nector, you may use a standard 25-pin to 9-pin
adapter. Table 1 shows the pinout of J3.
The MAX233 is an RS-232 interface voltage level shifter
with two transmitters and two receivers. It includes a
built-in charge pump with internal capacitors that gener-
ates the output voltages necessary to drive RS-232 lines.
Unregulated input voltage
+5V from on-board regulator
Chip select for 7E000–7E7FF
Chip select for 7E800–7EFFF
Chip select for 7F000–7F7FF
40-Pin Data Connector J1
The 20 x 2 pin header connects the 68HC16 module to
a Maxim EV kit. Table 2 lists the function of each pin.
Note that 68HC16 object code is not compatible with
68HC11 object code. Use the 68HC16 module only
with those modules that are designed to support it, and
only download code that is targeted for the 68HC16
module. Downloading incorrect object code into the
68HC16 module will have unpredictable results.
Chip select for 7F800–7FFFF
Address bit 0 (LSB)
Address bit 1
Address bit 2
Address bit 3
Buffered data bus 0 (LSB)
Buffered data bus bits 1–7
General I/O port bit 0 (LSB)
General I/O port bit 1
General I/O port bit 2
General I/O port bit 3
The 68HC16 µC generates various enable signals for dif-
General I/O port bit 4
ferent address ranges. The ROM and RAM enable sig-
General I/O port bit 5
nals are fed directly to the respective chips. Several
General I/O port bit 6
additional signals (J1.11–J1.14) are available on the data 34 IC4 General I/O port bit 7
connector to be used by Maxim EV kits. Table 3 outlines
QSPI master-in, slave-out
the address ranges for each of the elements found on
QSPI master-out, slave-in
the 68HC16 module, and Table 4 is a truth table that
QSPI serial clock
describes the logic for each of the 68HC16’s chip-select
38 PCS0/SS QSPI chip-select output
outputs. Because the addresses are not completely
decoded, the boot ROM and user RAM have shadows.
39 CLKOUT System clock output
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