and SRAM. AM42BDS640AG Datasheet

AM42BDS640AG SRAM. Datasheet pdf. Equivalent

Part AM42BDS640AG
Description Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
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AM42BDS640AG
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Am42BDS640AG
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Publication Number 26445 Revision B Amendment 0 Issue Date November 1, 2002



AM42BDS640AG
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PRELIMINARY
Am42BDS640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
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MCP Features
Power supply voltage of 1.65 to 1.95 volt
High performance
— Access time as fast as 70 ns
Package
— 93-Ball FBGA
Operating Temperature
— –40°C to +85°C
Power dissipation (typical values, CL = 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
HARDWARE FEATURES
Software command sector locking
Handshaking: host monitors operations via RDY output
Flash Memory Features
Hardware reset input (RESET#)
WP# input
ARCHITECTURAL ADVANTAGES
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
— Write protect (WP#) function protects sectors 0, 1 (bottom
boot) or sectors 132 and 133 (top boot), regardless of sector
protect status
Manufactured on 0.17 µm process technology
ACC input: Acceleration function reduces programming
Simultaneous Read/Write operation
time; all sectors locked when ACC = VIL
Data can be continuously
executing erase/program
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compatible
inputs,
CMOS
compatible
outputs
— Zero latency between read and write operations
Low VCC write inhibit
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Sector Architecture
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
Data# Polling and toggle bits
— Eight 8 Kword sectors and one hundred twenty-six 32
Erase Suspend/Resume
Kword sectors
— Suspends or resumes an erase operation in one sector to
— Banks A and D each contain four 8 Kword sectors and
read data from, or program data to, other sectors
thirty-one 32 Kword sectors; Banks B and C each contain
thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the address
range, and four at the bottom of the address range
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
Minimum 1 million erase cycle guarantee per sector
SRAM Features
20-year data retention at 125°C
PERFORMANCE CHARCTERISTICS
Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
— Asynchronous random access times of 70 ns (at 30 pF)
— Synchronous latency of 87.5/95 ns
Power dissipation
— Operating: 3 mA maximum
— Standby: 15 µA maximum
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.0 to 2.2 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
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This document contains information on a product under development at Advanced Micro Devices. The information
Publication# 26445 Rev: B Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
Issue Date: November 1, 2002
product without notice.
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Refer to AMD’s Website (www.amd.com) for the latest information.





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