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Phase-Frequency Detector. MC100EP40 Datasheet

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Phase-Frequency Detector. MC100EP40 Datasheet






MC100EP40 Detector. Datasheet pdf. Equivalent




MC100EP40 Detector. Datasheet pdf. Equivalent





Part

MC100EP40

Description

3.3V / 5V ECL Differential Phase-Frequency Detector



Feature


MC100EP40 3.3V / 5V ECL Differential Phase-Frequency Detector Description Th e MC100EP40 is a three−state phase− frequency detector intended for phase locked loop applications which require a minimum amount of phase and frequenc y difference at lock. Advanced design s ignificantly reduces the dead zone of t he detector. For proper operation, the input edge rate of the R a.
Manufacture

ON Semiconductor

Datasheet
Download MC100EP40 Datasheet


ON Semiconductor MC100EP40

MC100EP40; nd V inputs should be less than 5 ns. Th e device is designed to work with a 3.3 V / 5 V power supply. When Reference ( R) and Feedback (FB) inputs are unequal in frequency and/or phase the differen tial UP (U) and DOWN (D) outputs will p rovide pulse streams which when subtrac ted and integrated provide an error vol tage for control of a VCO. When Referen ce (R) and Feedbac.


ON Semiconductor MC100EP40

k (FB) inputs are 80 ps or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state (VOH ). The VTX (VTR, VTR, VTFB, VTFB) pins offer an internal termination network f or 50 W line impedance environment show n in Figure 2. An .


ON Semiconductor MC100EP40

.

Part

MC100EP40

Description

3.3V / 5V ECL Differential Phase-Frequency Detector



Feature


MC100EP40 3.3V / 5V ECL Differential Phase-Frequency Detector Description Th e MC100EP40 is a three−state phase− frequency detector intended for phase locked loop applications which require a minimum amount of phase and frequenc y difference at lock. Advanced design s ignificantly reduces the dead zone of t he detector. For proper operation, the input edge rate of the R a.
Manufacture

ON Semiconductor

Datasheet
Download MC100EP40 Datasheet




 MC100EP40
MC100EP40
3.3V / 5V ECL Differential
Phase-Frequency Detector
Description
The MC100EP40 is a three−state phase−frequency detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an
internal termination network for 50 W line impedance environment
shown in Figure 2. An external sinking supply of VCC−2 V is required
on VTX pin(s). If you short the two differential pins VTR and VTR (or
VTFB and VTFB) together, you provide a 100 W termination resistance.
For more information on termination of logic devices, see AND8020.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
For more information on Phase Lock Loop operation, refer to
AND8040.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
Features
Maximum Frequency > 2 GHz Typical
Fully Differential
Advanced High Band Output Swing of 400 mV
Theoretical Gain = 1.11
Trise 97 ps Typical, Ffall 70 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −5.5 V
50 W Internal Termination Resistor
These are Pb−Free Devices
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20
1
TSSOP−20
DT SUFFIX
CASE 948E
MARKING
DIAGRAM*
20
100
EP40
ALYW G
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 13
1
Publication Order Number:
MC100EP40/D




 MC100EP40
MC100EP40
VCC PLD VCC D D U U VCC NC VEE
20 19 18 17 16 15 14 13 12 11
123456
VEE VTFB VTFB FB FB R
7 8 9 10
R VTR VTR VBB
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 20−Lead Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
U, U
D, D
FB, FB
R, R
PLD
VTR
VTR
VTFB
VTFB
VBB
VCC
VEE
NC
FUNCTION
ECL Up Differential Outputs
ECL Down Differential Outputs
ECL Feedback Differential Inputs
ECL Reference Differential Inputs
ECL Phase Lock Detect Function
ECL Internal Termination for R
ECL Internal Termination for R
ECL Internal Termination for FB
ECL Internal Termination for FB
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
VTR
R
R
VTR
50 W
50 W
VTFB
(V) FB
FB
VTFB
VBB
50 W
50 W
U
A
AC
SU
Reset
FF
R
A
C
D
B
D
Reset R D
B FF
S
B
D
Figure 2. Logic Diagram
C
A
Reset
Reset
B
D
U
U
D
D
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2




 MC100EP40
MC100EP40
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−20
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 4 kV
> 100 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 3
UL 94 V−0 @ 0.125 in
699 Devices
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI v VCC
VI w VEE
6V
−6 V
6V
−6 V
50 mA
100 mA
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
± 0.5
−40 to +85
−65 to +150
140
100
mA
°C
°C
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case)
Standard Board
Tsol Wave Solder
Pb
Pb−Free
TSSOP−20
23 to 41
265
265
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3



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