AD9734 DACS Datasheet

AD9734 Datasheet PDF, Equivalent


Part Number

AD9734

Description

1200 MSPS DACS

Manufacture

Analog Devices

Total Page 30 Pages
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AD9734
10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
RESET
S1 S2 S3
IRQ
DACCLK– DACCLK+
SDIO
SDO
CSB
SCLK
C1
SPI CONTROLLER C2
C3 C3
DATACLK_OUT+
DATACLK_OUT–
CLOCK
DISTRIBUTION
S3
DATACLK_IN+
DATACLK_IN–
DB[13:0]+
DB[13:0]–
14-, 12-,
IOUTA
10-BIT DAC
CORE
IOUTB
C2 BAND GAP
C1S1
REFERENCE
CURRENT S2
VREF
I120
Figure 1.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2. Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3. Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4. Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5. The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

AD9734
AD9734/AD9735/AD9736
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
AC Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Location of Supply and Control Pins....................................... 16
Terminology .................................................................................... 17
Typical Performance Characteristics ........................................... 18
AD9736 Static Linearity, 10 mA Full Scale ............................. 18
AD9736 Static Linearity, 20 mA Full Scale ............................. 19
AD9736 Static Linearity, 30 mA Full Scale ............................. 20
AD9735 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 21
AD9734 Static Linearity, 10 mA, 20 mA, 30 mA
Full Scale...................................................................................... 22
AD9736 Power Consumption, 20 mA Full Scale....................... 23
AD9736 Dynamic Performance, 20 mA Full Scale................ 24
AD9735, AD9734 Dynamic Performance, 20 mA
Full Scale...................................................................................... 27
AD973x WCDMA ACLR, 20 mA Full Scale .......................... 28
SPI Register Map............................................................................. 29
SPI Register Details ........................................................................ 30
Mode Register (Reg. 0) .............................................................. 30
Interrupt Request Register (IRQ) (Reg. 1) .............................. 30
Full Scale Current (FSC) Registers (Reg. 2, Reg. 3)............... 31
LVDS Controller (LVDS_CNT) Registers
(Reg. 4, Reg. 5, Reg. 6) ............................................................... 31
SYNC Controller (SYNC_CNT) Registers
(Reg. 7, Reg. 8)............................................................................ 32
Cross Controller (CROS_CNT) Registers
(Reg. 10, Reg. 11)........................................................................ 32
Analog Control (ANA_CNT) Registers
(Reg. 14, Reg. 15)........................................................................ 33
Built-In Self Test Control (BIST_CNT) Registers
(Reg. 17, Reg. 18, Reg. 19, Reg. 20, Reg. 21)........................... 33
Controller Clock Predivider (CCLK_DIV) Reading
Register (Reg. 22) ....................................................................... 34
Theory of Operation ...................................................................... 35
Serial Peripheral Interface ............................................................. 36
General Operation of the Serial Interface............................... 36
Short Instruction Mode (8-Bit Instruction) ........................... 36
Long Instruction Mode (16-Bit Instruction).......................... 36
Serial Interface Port Pin Descriptions ..................................... 36
SCLK—Serial Clock............................................................... 36
CSB—Chip Select................................................................... 37
SDIO—Serial Data I/O.......................................................... 37
SDO—Serial Data Out .......................................................... 37
MSB/LSB Transfers .................................................................... 37
Notes on Serial Port Operation ................................................ 37
Pin Mode Operation .................................................................. 38
RESET Operation....................................................................... 38
Programming Sequence ............................................................ 38
Interpolation Filter..................................................................... 39
Data Interface Controllers......................................................... 39
LVDS Sample Logic.................................................................... 40
LVDS Sample Logic Calibration............................................... 40
Operating the LVDS Controller in Manual Mode via the
SPI Port ........................................................................................ 41
Rev. A | Page 2 of 72


Features 10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD 9735/AD9736 FEATURES Pin-compatible fa mily Excellent dynamic performance AD97 36: SFDR = 82 dBc at fOUT = 30 MHz AD97 36: SFDR = 69 dBc at fOUT = 130 MHz AD9 736: IMD = 87 dBc at fOUT = 30 MHz AD97 36: IMD = 82 dBc at fOUT = 130 MHz LVDS data interface with on-chip 100 Ω ter minations Built-in self test LVDS sampl ing integrity LVDS-to-DAC data transfer integrity Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz) 1.8/3.3 V dual-supp ly operation Adjustable analog output 8 .66 mA to 31.66 mA (RL = 25 Ω to 50 Ω ) On-chip 1.2 V reference 160-lead chip scale ball grid array (CSP_BGA) packag e APPLICATIONS Broadband communications systems Cellular infrastructure (digit al predistortion) Point-to-point wirele ss CMTS/VOD Instrumentation, automatic test equipment Radar, avionics GENERAL DESCRIPTION The AD9736, AD9735, and AD9 734 are high performance, high frequenc y DACs that provide sample rates of up to 1200 MSPS, permitting multicarrier generation up to their Ny.
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