Exceeds SONET requirements for jitter transfer/
Quantizer sensitivity: 3.3 mV typical
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV
Independent slice level adjust and LOS detector
No reference clock required
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 423 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
Broadband cross-connects and routers
622 Mbps Clock and Data Recovery IC
with Integrated Limiting Amplifier
The ADN2804 provides the receiver functions of quantization,
signal level detect, clock and data recovery, and data retiming
for 622 Mbps NRZ data. The ADN2804 automatically locks to
622 Mbps data without the need for an external reference clock
or programming. In the absence of input data, the output clock
drifts no more than ±5%. All SONET jitter requirements are
met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
The receiver’s front-end loss-of-signal (LOS) detector circuit
indicates when the input signal level falls below a user-adjustable
threshold. The LOS detect circuit has hysteresis to prevent chatter
at the output.
The ADN2804 is available in a compact 5 mm × 5 mm,
FUNCTIONAL BLOCK DIAGRAM
CF1 CF2 VCC VEE
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