Data Recovery. ADN2804 Datasheet

ADN2804 Recovery. Datasheet pdf. Equivalent


Analog Devices ADN2804
www.DataSheet4U.com
FEATURES
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 3.3 mV typical
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 423 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
622 Mbps Clock and Data Recovery IC
with Integrated Limiting Amplifier
ADN2804
GENERAL DESCRIPTION
The ADN2804 provides the receiver functions of quantization,
signal level detect, clock and data recovery, and data retiming
for 622 Mbps NRZ data. The ADN2804 automatically locks to
622 Mbps data without the need for an external reference clock
or programming. In the absence of input data, the output clock
drifts no more than ±5%. All SONET jitter requirements are
met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver’s front-end loss-of-signal (LOS) detector circuit
indicates when the input signal level falls below a user-adjustable
threshold. The LOS detect circuit has hysteresis to prevent chatter
at the output.
The ADN2804 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1 CF2 VCC VEE
SLICEP/SLICEN
PIN
NIN
2
QUANTIZER
FREQUENCY
DETECT
LOOP
FILTER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VCO
VREF
LOS
DETECT
DATA
RE-TIMING
2
2
THRADJ
LOS
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
Figure 1.
ADN2804
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.


ADN2804 Datasheet
Recommendation ADN2804 Datasheet
Part ADN2804
Description Clock and Data Recovery
Feature ADN2804; www.DataSheet4U.com 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier ADN2804.
Manufacture Analog Devices
Datasheet
Download ADN2804 Datasheet




Analog Devices ADN2804
www.DataSheet4U.com
ADN2804
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 4
Output and Timing Specifications ............................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
I2C Interface Timing and Internal Register Description........... 10
Terminology .................................................................................... 12
REVISION HISTORY
2/06—Revision 0: Initial Version
Jitter Specifications......................................................................... 13
Theory of Operation ...................................................................... 14
Functional Description.................................................................. 16
Frequency Acquisition............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust.................................................................................. 16
Loss-of-Signal (LOS) Detector ................................................. 16
Lock Detector Operation .......................................................... 17
SQUELCH Modes ...................................................................... 17
I2C Interface ................................................................................ 17
Reference Clock (Optional) ...................................................... 19
Applications Information .............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Rev. 0 | Page 2 of 24



Analog Devices ADN2804
www.DataSheet4U.com
ADN2804
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Offset
Input RMS Noise
QUANTIZER—AC CHARACTERISTICS
Data Rate
Output Clock Range
S11
Input Resistance
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS-OF-SIGNAL (LOS) DETECT
Loss-of-Signal Detect Range (see Figure 6)
Hysteresis (Electrical)
LOS Assert Time
LOS Deassert Time
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock to Data Mode
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Fine Readback
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
OPERATING TEMPERATURE RANGE
Conditions
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled (see Figure 27, Figure 28, and Figure 29)
223 − 1 PRBS, ac-coupled,1 BER = 1 × 10–10
BER = 1 × 10–10
Absence of input data
@ 622 MHz
Differential
SLICEP − SLICEN = ±0.5 V
SLICEP − SLICEN
DC level @ SLICEP or SLICEN
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
OC-12
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
DC-coupled 2
DC-coupled2
With respect to nominal
With respect to nominal
OC-12
OC-12
In addition to REFCLK accuracy
OC-12
Locked to 622.08 Mbps
Min
1.8
2.3
6
0.10
−0.95
VEE
14.9
2.6
6.2
4.1
3.0
–40
Typ
2.5
3.3
500
290
622
622 ± 5%
−15
100
0.65
0.11
1
16.7
3.5
6.9
6.1
500
400
1000
250
200
2.0
20.0
100
3.3
128
Max
2.8
2.0
2.8
0.13
+0.95
0.95
18.4
4.4
7.7
8.1
3.6
+85
Unit
V
V
V
mV p-p
μV
μV rms
Mbps
MHz
dB
Ω
pF
V/V
V
V
mV
mV
mV
dB
dB
ns
ns
ppm
ppm
μs
ms
ms
ppm
V
mA
°C
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2804 input stage.
Rev. 0 | Page 3 of 24





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