Analog-to-Digital Converter. AD9640 Datasheet

AD9640 Converter. Datasheet pdf. Equivalent


Analog Devices AD9640
FEATURES
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS
SFDR = 85 dBc to 70 MHz @ 125 MSPS
Low power: 750 mW @ 125 MSPS
SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3V CMOS output supply or 1.8 V LVDS
output supply
Integer 1 to 8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
14-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9640
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD
FD BITS/THRESHOLD
DETECT
SPI
VIN+A
VIN–A
VREF
SENSE
CML
RBIAS
VIN–B
VIN+B
SHA
REF
SELECT
ADC
PROGRAMMING DATA
SIGNAL
MONITOR
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
SHA
ADC
SIGNAL MONITOR
DATA
MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR
SYNC
DETECT
INTERFACE
D13A
D0A
CLK+
CLK–
DCOA
DCOB
D13B
D0B
AGND SYNC
FD(0:3)B
Figure 1.
SMI SMI SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
PRODUCT HIGHLIGHTS
1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6. A standard serial port interface that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and voltage reference mode.
7. Pin compatibility with the AD9627, AD9627-11, and the
AD9600 for a simple migration from 14 bits to 12 bits, 11
bits, or 10 bits.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.


AD9640 Datasheet
Recommendation AD9640 Datasheet
Part AD9640
Description Dual Analog-to-Digital Converter
Feature AD9640; FEATURES SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low powe.
Manufacture Analog Devices
Datasheet
Download AD9640 Datasheet




Analog Devices AD9640
AD9640* Product Page Quick Links
Last Content Update: 11/01/2016
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Evaluation Kits
• AD9640 Evaluation Board
Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-1234: Interfacing the ADL5534 Dual IF Gain Block to
the AD9640 High Speed ADC
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9640: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual
Analog-to-Digital Converter Data Sheet
Product Highlight
• Leading Inside Advertorials: Data Converter Function Can
Help Solve Cost and Size Design Challenges in 3G and 4G
Wireless Infrastructure
Tools and Simulations
• Visual Analog
• AD9640 IBIS Models
• AD9627/AD9640 S-Parameters
Reference Materials
Technical Articles
• Improve The Design Of Your Passive Wideband ADC
Front-End Network
• Matching An ADC To A Transformer
• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources
• AD9640 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9640 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
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Analog Devices AD9640
AD9640
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
ADC DC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105......................................................................... 5
ADC DC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150......................................................................... 6
ADC AC Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105......................................................................... 7
ADC AC Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ 150 ......................................................................... 8
Digital Specifications ................................................................... 9
Switching Specifications—AD9640ABCPZ-80,
AD9640BCPZ-80, AD9640ABCPZ-105, and
AD9640BCPZ-105 ..................................................................... 10
Switching Specifications—AD9640ABCPZ-125,
AD9640BCPZ-125, AD9640ABCPZ-150, and
AD9640BCPZ-150 ..................................................................... 11
Timing Specifications ................................................................ 12
Absolute Maximum Ratings.......................................................... 14
Thermal Characteristics ............................................................ 14
ESD Caution................................................................................ 14
Pin Configurations and Function Descriptions ......................... 15
Equivalent Circuits ......................................................................... 19
Typical Performance Characteristics ........................................... 20
Theory of Operation ...................................................................... 25
ADC Architecture ...................................................................... 25
Analog Input Considerations.................................................... 25
Voltage Reference ....................................................................... 27
Clock Input Considerations...................................................... 28
Power Dissipation and Standby Mode .................................... 30
Digital Outputs ........................................................................... 31
Timing ......................................................................................... 31
ADC Overrange and Gain Control.............................................. 32
Fast Detect Overview................................................................. 32
ADC Fast Magnitude ................................................................. 32
ADC Overrange (OR)................................................................ 33
Gain Switching............................................................................ 33
Signal Monitor ................................................................................ 35
Peak Detector Mode................................................................... 35
RMS/MS Magnitude Mode......................................................... 35
Threshold Crossing Mode......................................................... 36
Additional Control Bits ............................................................. 36
DC Correction ............................................................................ 36
Signal Monitor SPORT Output ................................................ 37
Built-In Self-Test (BIST) and Output Test .................................. 38
Built-In Self-Test (BIST)............................................................ 38
Output Test Modes..................................................................... 38
Channel/Chip Synchronization.................................................... 39
Serial Port Interface (SPI).............................................................. 40
Configuration Using the SPI..................................................... 40
Hardware Interface..................................................................... 40
Configuration Without the SPI ................................................ 41
SPI Accessible Features.............................................................. 41
Memory Map .................................................................................. 42
Reading the Memory Map Table.............................................. 42
External Memory Map .............................................................. 43
Memory Map Register Description ......................................... 46
Applications Information .............................................................. 49
Design Guidelines ...................................................................... 49
Outline Dimensions ....................................................................... 50
Ordering Guide .......................................................................... 51
Rev. B | Page 2 of 52







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