KM641001B SRAM Datasheet
|Total Page||9 Pages|
256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out.
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 17ns, L-version and Industrial Temperature Part.
2.3. Delete VOH1=3.95V.
2.4. Delete Data Retention Characteristics and Wave form.
2.5. Relex operating current.
3.1. Add Low power Version.
3.2. Add Data Retention chcracteristics.
Feb. 1st 1997
Jun. 1st 1997
Feb. 6th 1998 Final
Jul. 28th 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
1mA(Max) L-Ver. Only
Operating KM641001B/BL - 15 : 120mA(Max.)
KM641001B/BL - 20 : 118mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Standard Pin Configuration
KM641001B/BLJ : 28-SOJ-400A
The KM641001B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
KM641001B/BL uses 4 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM641001B/BL is pack-
aged in a 400 mil 28-pin plastic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION(Top View)
I/O Circuit &
A9 A10 A11 A12 A13 A14 A15 A16 A17
A0 - A17
I/O1 ~ I/O4
|Features||www.DataSheet4U.com PRELIMINARY CMOS SR AM KM641001B/BL Document Title 256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out. Rev ision History Rev. No. Rev. 0.0 Rev.1.0 History Initial release with Design Ta rget. Release to Preliminary Data Sheet . 1.1. Replace Design Target to Prelimi nary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 17ns, L-version and Industrial Temperature Pa rt. 2.3. Delete VOH1=3.95V. 2.4. Delete Data Retention Characteristics and Wav e form. 2.5. Relex operating current. S peed Previous Now 15ns 120mA 120mA 17ns 110mA 20ns 100mA 118mA 3.1. Add Low po wer Version. 3.2. Add Data Retention ch cracteristics. Draft Data Feb. 1st 1997 Jun. 1st 1997 Remark Design Target Pre liminary Rev. 2.0 Feb. 6th 1998 Fina l Rev.3.0 Jul. 28th 1998 Final The attached data sheets are prepared and a pproved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the righ t to change the specifications. SAMSUNG Electronics will evalua.|
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