A/D Converter. ADC081500 Datasheet

ADC081500 Converter. Datasheet pdf. Equivalent


National Semiconductor ADC081500
www.DataSheet4U.com
September 2005
ADC081500
High Performance, Low Power, 8-Bit, 1.5 GSPS A/D
Converter
General Description
The ADC081500 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits
resolution at sample rates up to 1.7 GSPS. Consuming a
typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this
device is guaranteed to have no missing codes over the full
operating temperature range. The unique folding and inter-
polating architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold ampli-
fier and the self-calibration scheme enable a very flat re-
sponse of all dynamic parameters beyond Nyquist, produc-
ing a high 7.3 ENOB with a 748 MHz input signal and a 1.5
GHz sample rate while providing a 10-18 B.E.R. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The converter output has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on each bus to
one-half the sample rate.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C TA +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 748 MHz Input
n DNL
n Power Consumption
— Operating
— Power Down Mode
8 Bits
1.5 GSPS (min)
10-18 (typ)
7.3 Bits (typ)
±0.15 LSB (typ)
1.2 W (typ)
3.5 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
© 2005 National Semiconductor Corporation DS201531
20153153
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ADC081500 Datasheet
Recommendation ADC081500 Datasheet
Part ADC081500
Description A/D Converter
Feature ADC081500; www.DataSheet4U.com ADC081500 High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter September.
Manufacture National Semiconductor
Datasheet
Download ADC081500 Datasheet




National Semiconductor ADC081500
Ordering Information
Industrial Temperature Range
(-40˚C < TA < +85˚C)
ADC081500CIYB
ADC081500EVAL
Pin Configuration
NS Package
128-Pin Exposed Pad LQFP
Evaluation Board
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
20153101
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National Semiconductor ADC081500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
3 OutV / SCLK
OutEdge / DDR
4
/ SDATA
15 DCLK_RST
26 PD
30 CAL
14 FSR/ECE
127 CalDly / SCS
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See Section 1.1.6. When the
extended control mode is enabled, this pin functions as the
SCLK input which clocks in the serial data. See Section 1.3
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. (See Section 1.1.5.2). When this pin is
floating or connected to 1/2 the supply voltage, DDR clocking
is enabled. When the extended control mode is enabled, this
pin functions as the (SDATA) input. See Section 1.2 for
details on the extended control mode.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outputs of multiple converters. See
Section 1.5 for detailed description.
Power Down Pin. A logic high on the PD pin puts the device
into the Power Down Mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles high
on this pin initiates the self calibration sequence. See Section
2.4.2.
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to 650 mVP-P. A logic high on
this pin sets the full-scale differential input range to 870
mVP-P. See Section 1.1.4. To enable the extended control
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to VA/2. See Section 1.2 for information on the
extended control mode.
Calibration Delay and Serial Interface Chip Select. With a
logic high or low on pin 14, this pin functions as Calibration
Delay and sets the number of input clock cycles after power
up before calibration begins (See Section 1.1.1). With pin 14
floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay).
18 CLK+
19 CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 2.3.
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