PC7447A microprocessor Datasheet

PC7447A Datasheet, PDF, Equivalent


Part Number

PC7447A

Description

PowerPC RISC microprocessor

Manufacture

ATMEL Corporation

Total Page 30 Pages
Datasheet
Download PC7447A Datasheet


PC7447A
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Features
3000 Dhrystone 2.1 MIPS at 1.3 GHz
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
PD Typically 18W at 1.33 GHz at VDD = 1.3V; 8.0W at 1 GHz at VDD = 1.1V
Full Operating Conditions
Nap, Doze and Sleep Power Saving Modes
Superscalar (Four Instructions Fetched Per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 Hexabytes (252)
64-bit Data and 36-bit Address Bus Interface
Integrated L1: 32 KB Instruction and 32 KB Data Cache
Integrated L2: 512 KB
11 Independent Execution Units and 3 Register Files
Write-back and Write-through Operations
fINT Max = 1.33 GHz (1.42 GHz to be Confirmed)
fBUS Max = 133 MHz/166 MHz
Description
The PC7447A host processor is a high-performance, low-power, 32-bit implementa-
tions of the PowerPC Reduced Instruction Set Computer (RISC) architecture
combined with a full 128-bit implementation of Freescale®’s AltiVectechnology.
This microprocessor is ideal for leading-edge embedded computing and signal pro-
cessing applications. The PC7447A features 512 KB of on-chip L2 cache. The
PC7447A microprocessor has no backside L3 cache, allowing for a smaller package
designed as a pin-for-pin replacement for the PC7447 microprocessor. This device
benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to
help deliver tremendous power savings without sacrificing speed. A low-power version
of the PC7447A microprocessor is also available.
Figure 1-1 shows a block diagram of the PC7447A. The core is a high-performance
superscalar design supporting a double-precision floating-point unit and a SIMD multi-
media unit. The memory storage subsystem supports the MPX bus protocol and a
subset of the 60x bus protocol to the main memory and other system resources.
Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447
application if the core power supply is 1.3V.
Screening
Full Military Temperature Range (Tj = -55°C, +125°C)
Industrial Temperature Range (Tj = -40°C, +110°C)
PowerPC®
7447A
RISC
Microprocessor
PC7447A
Preliminary
GH suffix
HITCE 360
Rev. 5387B–HIREL–07/05

PC7447A
Additional Features
• Time Base Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
Dynamic Frequency Switching (DFS)
Temperature Dioder
Completion Unit 96-Bit (3 Instructions)
Completion Queue
(16-Entry)
Instruction Unit
Branch Processing Unit
BTIC (128-Entry) CTR
Fetcher
BHT (2048-Entry) LR
Dispatch
Unit
VR Issue
(4-Entry/2-Issue)
GPR Issue
(6-Entry/3-Issue)
Instruction Queue
(12-Word)
FPR Issue
(2-Entry/1-Issue)
Instruction MMU
SRs 128-Entry
(Shadow) ITLB
IBAT Array
128-Bit (4 Instructions)
Tags
32-Kbyte
I Cache
Data MMU
SRs 128-Entry
(Original) DTLB
DBAT Array
Tags 32-Kbyte
D Cache
Completes up
to three
instructions
per clock
VR File
16 Rename
Reservation Reservation Reservation Reservation Buffers
Station Station Station Station
Reservation
Stations (2)
Integer
Unit 2
Vector
Permute
Unit
Vector
Integer
Unit 2
Vector
Integer
Unit 1
Vector
FPU
128-Bit
128-Bit
32-Bit
Reservation
Station
Integer
Unit 1
(3)
+
Vector
Touch
Queue
GPR File
16 Rename
Buffers
32-Bit
32-Bit
Reservation
Stations (2-Entry)
EA
Load/Store Unit
Vector Touch Engine
+ (EA Calculation)
Finished L1 Castout
Stores
PA
FPR File
16 Rename
Buffers
L1 Push
Reservation
Stations (2)
Floating-
Point Unit
+ x÷
Completed
Stores Load Miss 64-Bit 64-Bit
FPSCR
Memory Subsystem
L1 Store Queue
(LSQ)
L1 Load Queue (LLQ)
L1 Service
Queues
L1 Load Miss (5)
L2 Prefetch (3)
Instruction Fetch (2)
Cacheable Store Request (1)
512-Kbyte Unified L2 Cache Controller
Line Block 0 (32-Byte) Block 1 (32-Byte)
Tags Status
Status
L2 Store Queue (L2SQ)
L1 Castouts
(4)
Snoop Push/
Interventions
Notes: The castout queue and push queue share resources such for a combined total of entries.
The castout queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.
System Bus Interface
Load
Queue (11)
Bus Store Queue
Castout
Queue (9) /
Push
Queue (10)2
Bus Accumulator
36-bit
Address Bus
64-bit
Data Bus


Features www.DataSheet4U.com Features • • • • • • • • • • • • • 3000 Dhrystone 2.1 MIPS at 1 .3 GHz Selectable Bus Clock (30 CPU Bus Dividers up to 28x) Selectable MPx/60x Interface Voltage (1.8V, 2.5V) PD Typi cally 18W at 1.33 GHz at VDD = 1.3V; 8. 0W at 1 GHz at VDD = 1.1V Full Operatin g Conditions Nap, Doze and Sleep Power Saving Modes Superscalar (Four Instruct ions Fetched Per Clock Cycle) 4 GB Dire ct Addressing Range Virtual Memory: 4 H exabytes (252) 64-bit Data and 36-bit A ddress Bus Interface Integrated L1: 32 KB Instruction and 32 KB Data Cache Int egrated L2: 512 KB 11 Independent Execu tion Units and 3 Register Files Write-b ack and Write-through Operations fINT M ax = 1.33 GHz (1.42 GHz to be Confirmed ) fBUS Max = 133 MHz/166 MHz PowerPC® 7447A RISC Microprocessor PC7447A Prel iminary Description The PC7447A host p rocessor is a high-performance, low-pow er, 32-bit implementations of the Power PC Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implement.
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