Interface Adapter. A6850 Datasheet

A6850 Adapter. Datasheet pdf. Equivalent

Part A6850
Description Asynchronous Communications Interface Adapter
Feature www.DataSheet4U.com a6850 ® Asynchronous Communications Interface Adapter Data Sheet September 19.
Manufacture Altera Corporation
Datasheet
Download A6850 Datasheet



A6850
September 1996, ver. 1
www.DataSheet4U.com
a6850
® Asynchronous Communications
Interface Adapter
Data Sheet
Features
General
Description
s a6850 MegaCore function implementing an asychronous
communications interface adapter (ACIA)
s Optimized for FLEX® and MAX® architectures
s Programmable word lengths, stop bits, and parity
s Offers divide-by-1, -16, or -64 mode
s Includes error detection
s Uses approximately 237 FLEX logic elements (LEs)
s Functionally based on the Motorola MC6850 device, except as noted
in the “Variations & Clarifications” section on page 94
The a6850 MegaCore function implements an ACIA, which is a universal
asynchronous receiver/transmitter (UART). The a6850 provides an
interface between a microprocessor and a serial communications channel.
The a6850 receives and transmits data in a variety of configurations,
including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2
stop bits. See Figure 1.
Figure 1. a6850 Symbol
nCTS
A6850
nDCD
E
nRESET
nIRQ
RS nRTS
RnW
TXDATA
RXCLK
DO[7..0]
RXDATA
TXCLK
CS[2..0]
DI[7..0]
Altera Corporation
A-DS-A6850-01
81



A6850
a6850 Asynchronous Communications Interface Adapter Data Sheet
Table 1 describes the input and output ports of the a6850.
Table 1. a6850 Ports
Name
ncts
Type
Input
ndcd
Input
e
nreset
rs
Input
Input
Input
rnw Input
rxclk
Input
rxdata
txclk
cs[2..0]
di[7..0]
nirq
nrts
Input
Input
Input
Input
Output
Output
txdata
do[7..0]
Output
Output
Polarity
Low
Low
High
Low
Low
Low
Low
Description
Clear to send, a modem signal name. The ncts input inhibits the
assertion of the transmit data register empty (tdre) status bit.
Data carrier detect, a modem signal name. When the ndcd signal
transitions from low to high, an interrupt to the microprocessor is
generated.
Enable for the microprocessor interface. When e is high, the
microprocessor can access the registers.
Asynchronous reset for the registers and control logic. The nreset
pin was not included in the original MC6850 device.
Register select. This input selects the register based on rnw. If rnw
is high (signaling a read operation), then rs = 1 selects the receiver
data register and rs = 0 selects the status register. However, if rnw
is low (signaling a write operation), then rs = 1 selects the
transmitter data register and rs = 0 selects the control register.
Read/write register controls. When rnw is high, the microprocessor
reads the registers; when rnw is low, the microprocessor writes to
the registers.
Receive clock. The receive control register samples rxdata based
on rxclk and the state of the counter divide select (cds) bits in the
control register.
Receive data. Serial data input from the modem or peripheral.
Transmit clock. Data is asserted to txdata on the falling edge of
txclk.
Chip select from the microprocessor. Chip select must be in the 110
state for the a6850 to be selected.
Parallel data input from the microprocessor or other controlling
device.
Interrupt request to microprocessor.
Request to send. Bits 5 and 6 (transmitter control bits) of the control
register set the nrts bit. The nrts signal is asserted when bit 6 is
low, or bits 5 and 6 are both high.
Transmit data. Serial output to the modem or peripheral.
Parallel data output to the microprocessor or other controlling device.
82 Altera Corporation





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