Edge-Triggered Flip-Flop. 54ACT112 Datasheet

54ACT112 Flip-Flop. Datasheet pdf. Equivalent

Part 54ACT112
Description Dual JK Negative Edge-Triggered Flip-Flop
Feature www.DataSheet4U.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop September 1998 54ACT112 Du.
Manufacture National Semiconductor
Datasheet
Download 54ACT112 Datasheet



54ACT112
www.DataSheet4U.com
September 1998
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on SD and CD force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n ’ACT112 has TTL-compatible inputs
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram
Pin Assigment for
DIP and Flatpack
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
(Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
DS100976-3
Pin Assigment
for LCC
DS100976-5
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100976
www.national.com



54ACT112
Logic Symbols
DS100976-1
IEEE/IEC
DS100976-2
DS100976-4
Truth Table
Inputs
Outputs
SD CD CP J K
L H X XX
Q
H
Q
L
H L X XX L H
L L X XX H H
H H M h h Q0 Q0
H H M lh L H
H H Mhl H L
H H M l l Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
M = HIGH-to-LOW Clock Transition
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock
transition.
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