Voltage Monitor. X40420 Datasheet

X40420 Datasheet PDF, Equivalent


Part Number

X40420

Description

(X40420 / X40421) Dual Voltage Monitor

Manufacture

Intersil Corporation

Total Page 25 Pages
PDF Download
Download X40420 Datasheet PDF


X40420 Datasheet
®
PRELIMINARY
Data Sheet
X40420, X40421
4kbit EEPROM
March 28, 2005
FN8117.0
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 Programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery Switch Backup
• VOUT: 5mA to 50mA from VCC; or 250µA from
VBATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• •Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• VOUT 5mA to 50mA
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
X40420/21
Standard VTRIP1 Level Standard VTRIP2 Level
4.6V (+/-1%)
2.9V(+/-1.7%)
4.6V (+/-1%)
2.6V (+/-2%)
2.9V(+/-1.7%)
1.6V (+/-3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock
protect serial EEPROM in one package. This combi-
nation lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
V2 Monitor
Logic
VOUT
+
VTRIP2
-
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Watchdog
and
Reset Logic
VOUT
Power-on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

X40420 Datasheet
X40420, X40421
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares VCC with VBATT input
and connects VOUT to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40420/21 can drive
50mA from VCC to 250µA from VBATT. The device only
switches to VBATT when VCC drops below the low VCC
voltage threshold and VBATT.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Example Application
Unreg.
Supply
5V
REG
BATT-ON
VCC
VBATT VOUT
+
X40420/21
V2MON
V2FAIL
VDO
RESET
MR
SCL SDA
Enable
SRAM
Addr
Manual
Reset
Addr
uC
NMI
IRQ
VCC
RESET
I2C
PIN CONFIGURATION
X40420
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
X40421
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 BATT-ON
12 VOUT
11 VBATT
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used.
3 LOWLINE Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1.
When VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor.
4 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain
HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up resistor.
2 March 28, 2005


Features Datasheet pdf ® X40420, X40421 4kbit EEPROM Data She et March 28, 2005 FN8117.0 PRELIMINARY Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switc h FEATURES • Dual voltage detection a nd reset assertion —Three standard re set threshold settings (4.6V/2.9V, 4.6V /2.6V, 2.9V/1.6V) —VTRIP2 Programmabl e down to 0.9V —Adjust low voltage re set threshold voltages using special pr ogramming sequence —Reset signal vali d to VCC = 1V —Monitor two voltages o r detect power fail • Battery Switch Backup • VOUT: 5mA to 50mA from VCC; or 250µA from VBATT • Fault detectio n register • Selectable power-on rese t timeout (0.05s, 0.2s, 0.4s, 0.8s) • Selectable watchdog timer interval (25 ms, 200ms, 1.4s, off) • Debounced man ual reset input • Low power CMOS —2 5µA typical standby current, watchdog on —6µA typical standby current, wat chdog off —1µA typical battery curre nt in backup mode www.DataSheet4U.com 4Kbits of EEPROM —16 byte page write mode —Self-timed write cycle —5ms write cycle time (typical) •.
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