Digital-to-Analog Converter. DAC124S085 Datasheet

DAC124S085 Converter. Datasheet pdf. Equivalent

DAC124S085 Datasheet
Recommendation DAC124S085 Datasheet
Part DAC124S085
Description 12-Bit Micro Power QUAD Digital-to-Analog Converter
Feature DAC124S085; DAC124S085 12-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output January 200.
Manufacture National Semiconductor
Datasheet
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National Semiconductor DAC124S085
January 2007
DAC124S085
12-Bit Micro Power QUAD Digital-to-Analog Converter with
Rail-to-Rail Output
General Description
The DAC124S085 is a full-featured, general purpose QUAD
12-bit voltage-output digital-to-analog converter (DAC) that
can operate from a single +2.7V to 5.5V supply and consumes
1.1 mW at 3V and 2.4 mW at 5V. The DAC124S085 is pack-
aged in 10-lead LLP and MSOP packages. The 10-lead LLP
package makes the DAC124S085 the smallest QUAD DAC
in its class. The on-chip output amplifier allows rail-to-rail out-
put swing and the three wire serial interface operates at clock
rates up to 40 MHz over the entire supply voltage range.
Competitive devices are limited to 25 MHz clock rates at sup-
ply voltages in the 2.7V to 3.6V range. The serial interface is
compatible with standard SPI, QSPI, MICROWIRE and
DSP interfaces.
The reference for the DAC124S085 serves all four channels
and can vary in voltage between 1V and VA, providing the
widest possible output dynamic range. The DAC124S085 has
a 16-bit input shift register that controls the outputs to be up-
dated, the mode of operation, the powerdown condition, and
the binary input data. All four outputs can be updated simul-
taneously or individually depending on the setting of the two
mode of operation bits.
A power-on reset circuit ensures that the DAC output powers
up to zero volts and remains there until there is a valid write
to the device. A power-down feature reduces power con-
sumption to less than a microWatt with three different termi-
nation options.
The low power consumption and small packages of the
DAC124S085 make it an excellent choice for use in battery
operated equipment.
The DAC124S085 is one of a family of pin compatible DACs,
including the 8-bit DAC084S085 and the 10-bit DAC104S085.
The DAC124S085 operates over the extended industrial tem-
perature range of −40°C to +105°C.
Features
Guaranteed Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to 0V
Simultaneous Output Updating
Wide power supply range (+2.7V to +5.5V)
Industry's Smallest Package
Power Down Modes
Key Specifications
Resolution
INL
DNL
Settling Time
Zero Code Error
Full-Scale Error
Supply Power
Normal
Power Down
12 bits
±8 LSB (max)
+0.7 / −0.5 LSB (max)
8.5 µs (max)
+15 mV (max)
−0.75 %FS (max)
1.1 mW (3V) / 2.4 mW (5V) typ
0.3 µW (3V) / 0.8 µW (5V) typ
Applications
Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Pin Configuration
20173201
SPIis a trademark of Motorola, Inc.
© 2007 National Semiconductor Corporation
201732
20173202
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National Semiconductor DAC124S085
Ordering Information
Order Numbers
DAC124S085CISD
DAC124S085CISDX
DAC124S085CIMM
DAC124S085CIMMX
DAC124S085EVAL
Temperature Range
−40°C TA +105°C
−40°C TA +105°C
−40°C TA +105°C
−40°C TA +105°C
Block Diagram
Package
LLP
LLP Tape-and-Reel
MSOP
MSOP Tape-and-Reel
Evaluation Board (MSOP)
Top Mark
X67C
X67C
X66C
X66C
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National Semiconductor DAC124S085
Pin Descriptions
LLP
MSOP
Pin No.
1
2
3
4
5
6
7
Symbol
VA
VOUTA
VOUTB
VOUTC
VOUTD
GND
VREFIN
8 DIN
9 SYNC
10 SCLK
11
PAD
(LLP only)
Type
Description
Supply
Analog Output
Analog Output
Analog Output
Analog Output
Ground
Analog Input
Digital Input
Digital Input
Digital Input
Ground
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
Channel B Analog Output Voltage.
Channel C Analog Output Voltage.
Channel D Analog Output Voltage.
Ground reference for all on-chip circuitry.
Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling
edges of SCLK after the fall of SYNC.
Frame synchronization input for the data input. When this pin goes low,
it enables the input shift register and data is transferred on the falling
edges of SCLK. The DAC is updated on the 16th clock cycle unless
SYNC is brought high before the 16th clock, in which case the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the
DAC.
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
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