A/D Converter. ADC14155 Datasheet

ADC14155 Converter. Datasheet pdf. Equivalent

Part ADC14155
Description 1.1 GHz Bandwidth A/D Converter
Feature ADC14155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter May 2007 ADC14155 14-Bit, 155 MSPS, 1.1.
Manufacture National Semiconductor
Datasheet
Download ADC14155 Datasheet



ADC14155
May 2007
ADC14155
14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter
General Description
The ADC14155 is a high-performance CMOS analog-to-dig-
ital converter capable of converting analog input signals into
14-bit digital words at rates up to 155 Mega Samples Per
Second (MSPS). This converter uses a differential, pipelined
architecture with digital error correction and an on-chip sam-
ple-and-hold circuit to minimize power consumption and the
external component count, while providing excellent dynamic
performance. A unique sample-and-hold stage yields a full-
power bandwidth of 1.1 GHz. The ADC14155 operates from
dual +3.3V and +1.8V power supplies and consumes 967 mW
of power at 155 MSPS.
The separate +1.8V supply for the digital output interface al-
lows lower power operation with reduced noise. A power-
down feature reduces the power consumption to 5 mW with
the clock input disabled, while still allowing fast wake-up time
to full operation.
The differential inputs provide a full scale differential input
swing equal to 2 times the reference voltage. A stable 1.0V
internal voltage reference is provided, or the ADC14155 can
be operated with an external reference.
The ADC14155 can be configured for either single-ended or
differential operation. Clock mode (differential versus single-
www.DataSheet4U.com ended) and output data format (offset binary versus 2's com-
plement) are pin-selectable. A duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead LLP package and
operates over the industrial temperature range of −40°C to
+85°C.
Features
1.1 GHz Full Power Bandwidth
Internal sample-and-hold circuit
Low power consumption
Internal precision 1.0V reference
Single-ended or Differential clock modes
Data Ready output clock
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V supply operation (+/- 10%)
Power-down mode
Offset binary or 2's complement output data format
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)
Key Specifications
Resolution
Conversion Rate
SNR (fIN = 70 MHz)
SFDR (fIN = 70 MHz)
ENOB (fIN = 70 MHz)
Full Power Bandwidth
Power Consumption
14 Bits
155 MSPS
71.3 dBFS (typ)
87.0 dBFS (typ)
11.5 bits (typ)
1.1 GHz (typ)
967 mW (typ)
Applications
High IF Sampling Receivers
Wireless Base Station Receivers
Power Amplifier Linearization
Multi-carrier, Multi-mode Receivers
Test and Measurement Equipment
Communications Instrumentation
Radar Systems
Block Diagram
© 2007 National Semiconductor Corporation 201790
20179002
www.national.com



ADC14155
Connection Diagram
Ordering Information
Industrial (−40°C TA +85°C)
ADC14155CISQ
ADC14155EB
20179001
Package
48 Pin LLP
Evaluation Board
www.national.com
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