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Signal Controllers. 56F826 Datasheet

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Signal Controllers. 56F826 Datasheet






56F826 Controllers. Datasheet pdf. Equivalent




56F826 Controllers. Datasheet pdf. Equivalent





Part

56F826

Description

16-bit Digital Signal Controllers



Feature


56F826 Data Sheet Preliminary Technical Data www.DataSheet4U.com 56F800 16-bi t Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale.com 56F826 General Description • • • • Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C- efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and cont.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F826 Datasheet


Freescale Semiconductor 56F826

56F826; roller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-b it words (64KB) Program Flash 512 × 16 -bit words (1KB) Program RAM 2K × 16-b it words (4KB) Data Flash 4K × 16-bit words (8KB) Data RAM 2K × 16-bit words (4KB) BootFLASH Up to 64K × 16-bit wo rds each of external memory expansion f or Program and Data memory • • • • • • • • One Serial Port Inte.


Freescale Semiconductor 56F826

rface (SPI) One additional SPI or two op tional Serial Communication Interfaces (SCI) One Synchronous Serial Interface (SSI) One General Purpose Quad Timer JT AG/OnCE™ for debugging 100-pin LQFP P ackage 16 dedicated and 30 shared GPIO Time-of-Day (TOD) Timer • • • • • EXTBOOT RESET IRQA IRQB 6 JT AG/ OnCE Port TOD Timer Interrupt Contr oller Program Controller and Har.


Freescale Semiconductor 56F826

dware Looping Unit Address Generation Un it Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bi t Accumulators Bit Manipulation Unit VD D 3 VSS 4 4 VDDIO VSSIO 4 Analog Reg VD DA VSSA Low Voltage Supervisor 4 Qua d Timer or GPIO Program Memory 32252 x 16 Flash 512 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 4096 x 16 SRAM PAB.

Part

56F826

Description

16-bit Digital Signal Controllers



Feature


56F826 Data Sheet Preliminary Technical Data www.DataSheet4U.com 56F800 16-bi t Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale.com 56F826 General Description • • • • Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C- efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and cont.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F826 Datasheet




 56F826
56F826
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
www.DataSheet4U.com
DSP56F826
Rev. 14
01/2007
freescale.com




 56F826




 56F826
56F826 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 4K × 16-bit words (8KB) Data RAM
• 2K × 16-bit words (4KB) BootFLASH
• Up to 64K × 16-bit words each of external memory
expansion for Program and Data memory
• One Serial Port Interface (SPI)
• One additional SPI or two optional Serial
Communication Interfaces (SCI)
• One Synchronous Serial Interface (SSI)
• One General Purpose Quad Timer
• JTAG/OnCEfor debugging
• 100-pin LQFP Package
• 16 dedicated and 30 shared GPIO
• Time-of-Day (TOD) Timer
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VDD
3
VSS
4
VDDIO VSSIO
44
VDDA
VSSA
Low Voltage Supervisor
Analog Reg
TOD
Timer
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Program Memory
Quad Timer
32252 x 16 Flash
4
or
GPIO
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
SSI
or
6 GPIO
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
SCI0 & SCI1
or
4 SPI0
COP/
Watchdog
SPI1
or
Applica-
4
GPIO
tion-Specific
Dedicated
GPIO
16
Memory &
Peripherals
PAB
PDB
COP
RESET
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
16
IPBB
CONTROLS
16
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
CLKO
XTAL
EXTAL
External
Address Bus
Switch
A[00:15]
16
or
GPIO
External
Bus
Interface
Unit
External
Data Bus
Switch
Bus
Control
D[00:15]
16
PS Select[0]
DS Select[1]
WR Enable
RD Enable
56F826 Block Diagram
Freescale Semiconductor
56F826 Technical Data, Rev. 14
3






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