16 BIT. MBM29DS163BE Datasheet

MBM29DS163BE BIT. Datasheet pdf. Equivalent

Part MBM29DS163BE
Description (MBM29DS163BE/TE) FLASH MEMORY CMOS 16 M (2 M X 8/1 M X 16) BIT
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20891-4E FLASH MEMORY CMOS 16 M (2 M ×.
Manufacture Fujitsu Media Devices
Datasheet
Download MBM29DS163BE Datasheet



MBM29DS163BE
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20891-4E
FLASH MEMORY
CMOS
16 M (2 M × 8/1 M × 16) BIT Dual Operation
MBM29DS163TE/BE10
s DESCRIPTION
The MBM29DS163TE/BE is 16 M-bit, 1.8 V-only Flash memory organized as 2 M bytes of 8 bits each or 1 M
words of 16 bits each. The device is offered in 48-pin TSOP (1) and 48-ball FBGA packages. This device is
designed to be programmed in system with standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not
required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
(Continued)
s PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29DS163TE/BE10
VCC
=
2.0
V +0.2
0.2
V
V
100
100
35
s PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
48-ball plastic FBGA
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-48P-M11)



MBM29DS163BE
MBM29DS163TE/BE10
(Continued)
The device is organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory
arrays as far as certain operations are concerned. This device is the same as Fujitsu’s standard 1.8 V only Flash
memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of
the array while an embedded write (either a program or an erase) operation is simultaneously taking place on
the other bank.
The standard device offers access time 100 ns, allowing operation of high-speed microprocessors without wait
state. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output
enable (OE) controls.
The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verify proper cell
margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed,
the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the
Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode
and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
2





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)