16 BIT. MBM29SL800TE Datasheet

MBM29SL800TE BIT. Datasheet pdf. Equivalent

Part MBM29SL800TE
Description (MBM29SL800TE/BE) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20911-1E FLASH MEMORY CMOS 8 M (1 M × .
Manufacture Fujitsu Media Devices
Datasheet
Download MBM29SL800TE Datasheet



MBM29SL800TE
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8 M (1 M × 8/512 K × 16) BIT
MBM29SL800TE/BE-90/10
DS05-20911-1E
s DESCRIPTION
The MBM29SL800TE/BE are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TE/BE are offered in a 48-ball FBGA and 45-ball SCSP packages.
These devices are designed to be programmed in-system with the standard system 1.8 V VCC supply. 12.0 V VPP
and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
s PRODUCT LINE UP
(Continued)
Part No.
VCC
Max Address Access Time
Max CE Access Time
Max OE Access Time
MBM29SL800TE/BE-90
MBM29SL800TE/BE-10
1.65 V to 1.95 V
90 ns
100 ns
90 ns
100 ns
30 ns
35 ns
s PACKAGES
48-ball Plastic FBGA
45-ball Plastic SCSP
(BGA-48P-M20)
(WLP-45P-M02)



MBM29SL800TE
MBM29SL800TE/BE-90/10
(Continued)
The standard MBM29SL800TE/BE offer access times 90 ns and 100 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) ,
write enable (WE) , and output enable (OE) controls.
The device supports pin and command set compatible with JEDEC standard E2PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell
margin.
Each sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL800TE/BE are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally returns to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29SL800TE/BE memories electrically erase the
entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are pro-
grammed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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