Field Memory. MSM5424331 Datasheet

MSM5424331 Memory. Datasheet pdf. Equivalent

Part MSM5424331
Description Field Memory
Feature www.DataSheet4U.com FEDS5424331-01 1 Semiconductor MSM5424331 222,720-Word × 24-Bit Field Memory .
Manufacture OKI electronic
Datasheet
Download MSM5424331 Datasheet




MSM5424331
www.DataSheet4U.com
FEDS5424331-01
1Semiconductor
MSM5424331
222,720-Word × 24-Bit Field Memory
This version: Sep. 2000
GENERAL DESCRIPTION
The MSM5424331 is an image data processing field memory organized as 222,720 (768 pixels by 290 lines) by 24
bits that can switch between the FIFO mode where the MSM5424331 is used as an ordinary field memory and a
block access mode where the MSM5424331 can easily exchange data with personal computer and the like.
Serial writing in and serial reading from the MSM5424331 are performed line by line. In the FIFO mode, any line
can be selected by specifying their addresses by the Serial Address input. In the Block Access mode, any line or
word address (10 bits) can be set by entering the address through the address multiplexer.
As the MSM5424331 in the Block Access mode can be controlled by RAS and CAS signals, it can easily interface
to the MPU.
The MSM5424331 contains dynamic memory cells. In the FIFO mode, the memory cells are automatically
refreshed by the self refresh control circuit, but in the Block Access mode, the memory cells must be refreshed by
the CAS before RAS Refresh function.
The MSM5424331 is not designed for high end use in such applications as medical systems, professional graphics
systems which require long term picture storage, data storage systems and others.
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MSM5424331
www.DataSheet4U.com
1Semiconductor
FEDS5424331-01
MSM5424331
FEATURES
Switching between FIFO and Block Access modes by the D/F pin
FIFO mode:
Serial write/read operation by line-by-line accessing
Block Access mode: Fast write/read operation on an 8-word basis by the RAS and CAS control
Organization of 768 × 290 × 24 bits
FIFO mode: Input × 12 or × 24 controlled by L/UWE
Output × 24
Block Access mode: Input × 12 (Two 768 × 290 × 12-bit banks are controlled by L/UWE.)
Output × 12 (Two 768 × 290 × 12-bit banks are controlled by A9.)
Asynchronous operation
Input and output asynchronous operation enabled only in the FIFO mode Single write or read operation in the
Block Access mode
Serial Read and Write Cycle times (in both the FIFO mode and the Block Access mode)
Cycle time: 60 ns
Access time: 50 ns
Operating supply voltage: 2.8 to 3.3 V
Refresh
FIFO mode:
Self refresh
Block Access mode: by the CAS before RAS refresh function (290 cycles/8 ms)
Address input
FIFO mode:
Setting random line address by the serial address input
Block Access mode: Setting random address in the address multiplexer by the RAS and CAS control
Selectable serial address input setting or various address resetting in the FIFO mode
Package:
70-pin 400 mil plastic TSOP (Type 2) (TSOP(2)70-P-400-0.50-K) (Product: MSM5424331TS-AK)
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