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xr
FEBRUARY 2006
PRELIMINARY
XRK39351
REV. P1.0.0
3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
input is pulled low. This is a test mode intended for system debug purposes. The XRK39351 has an output/input frequency range of 25MHz to 200MHz with the PLL enabled and an input frequency range of 2MHz to 300MHz when the PLL is disabled (test mo...
