POWER PREAMPLIFIER. L6316 Datasheet
4-CHANNEL LOW POWER PREAMPLIFIER
■ Dual Power Supplies of +5V, 10% and -3v, 6%
■ Low Power consumption; 980 mW @ 800Mb/s
(Single Head 100% Write mode duty cycle,
Random pattern, Iw = 40mA, Max Ovs).
■ Flip Chip package.L6316
■ Differential Voltage Bias / Voltage Sense
architecture. Current Bias available
■ Programmable read input differential
■ Selectable read path bandwidth from 200 to
>600 MHz (Rmr=40Ω). (Parameter dependent
■ Selectable LF corner (1, 2.5, 3.5 or 5.5 MHz with
■ Noise Figure of merit; 2.2 dB (Rmr=40Ω)
■ MR bias voltage programmable from 70 to 225
mV nom. (5 bits) (7.2mA max).
■ MR bias current programmable from 0.65 to
7.2 mA nom. (5 bits) (225mV max).
■ Read input stage optimized for MR resistance
from 20 to 70 Ohm.
■ Programmable read voltage gain of 37, 40, 43,
46 dB Rmr = 40Ω, Rload = 100Ω
■ Fully Differential write driver: Programmable
overshoot amplitude (3bits) and duration (2bits).
■ Write current rise/fall time with custom head and
interconnect model 140 pS at 40 mA (10% to
90%) (Steady state to steady state)
■ Write current amplitude programmable (5 bits) 0
to 62 mA (0-pk).
■ Bi-directional 16-bit serial interface 2.5V and
3.3V CMOS compatible.
■ 2-pin (RXW and TFI), 2 bits mode selection
■ All control signals are 2.5 & 3.3V CMOS
■ Analog buffered head voltage ABHV (gain of 5)
■ Automatic digital MR resistance measurement
■ Read head open detection, Read head shorted
■ Write head open or shorted to ground, Writer to
Reader short, write data frequency too low
■ SAFEDETECT method for write fault detection.
Figure 1. Package
Table 1. Order Codes
■ Low VCC or VEE supply & die over temperature
detect, Analog Temperature Measurement.
■ Fast write-to-read recovery 150nS (max) (same
■ Head-to-head switch in read mode 1.5us (nom).
■ Zero MR bias, very low power (43mW) idle mode
with fast recovery to read mode 1.5us (nom).
■ MR bias switching without overshoot for head
■ Read-to-Write switching 50nS (max) (same
■ ESD diodes for MR head protection
The L6316 is a BICMOS Silicon Germanium inte-
grated circuit differential preamplifier. It is de-
signed for use with four-terminal MR read and in-
ductive write heads. In read mode, the device
consists of a fully differential amplifier, offering;
voltage or current bias, voltage-sense input, pro-
grammable input impedance, low noise and high
bandwidth. In write mode, it includes fast current
switching differential write drivers, which support
data rates up to 1200 Mb/s.
This preamplifier provides programmable read
voltage or current bias and write current (5 bit
DACs for the read bias and for the write current),
fault detection circuitry and servo track writing fea-
tures. Read amplifier gain, low corner frequency,
and write current wave shape are adjustable. The
amplitude and duration of the overshoot are sepa-
rately programmable through a 16-bit bi-direction-
al serial interface (SEN, SDATA, and SCLK). The
device operates from +5V and -3V supplies.
This is preliminary information on a new product now in development. Details are subject to change without notice.
Figure 2. Preamplifier Block Diagram
Low supply detection,
Low write frequency,
Low pass filter
Figure 3. Flip Chip Pinout Diagram - BUMPS DOWN
Note: Minimum pad pitch = 204 um and pad opening (octagonal) = 70 um
Bump Sequence (see next table for coordinates)
TF VEE GND VCC
VEE GND VREF VCC
Minimum distance between pads opening center to center:
Die center misalignment w.r.t original die center after cut:
Bump material if eutectic:
Bump material if lead free:
X = 2192 ±20 um
Y = 2686 ±20 um
500 ±20 um
90 ±15 um
120 ±15 um
63% Tin, 37% Lead
96% Tin, 3.5% Silver, 0.5% Copper
Note: VREF PAD can be left floating or grounded. DO NOT CONNECT IT ANYWHERE ELSE.