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Up/Down Counter. MC14510B Datasheet

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Up/Down Counter. MC14510B Datasheet






MC14510B Counter. Datasheet pdf. Equivalent




MC14510B Counter. Datasheet pdf. Equivalent





Part

MC14510B

Description

BCD Up/Down Counter

Manufacture

Motorola

Datasheet
Download MC14510B Datasheet


Motorola MC14510B

MC14510B; www.DataSheet4U.com SEMICONDUCTOR TECHNI CAL DATA MOTOROLA MC14510B BCD Up/Dow n Counter The MC14510B synchronous up/ down BCD counter is constructed with MO S P–channel and N–channel enhanceme nt mode devices in a monolithic structu re. The counter consists of type D flip –flop stages with a gating structure to provide type T flip–flop capabilit y. This counter can be pre.


Motorola MC14510B

set by applying the desired value in BCD to the Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE ) high. The direction of counting is co ntrolled by applying a high (for up cou nting) or a low (for down counting) to the UP/DOWN input. The state of the cou nter changes on the positive transition of the clock input. Cascading can be a ccomplished by con.


Motorola MC14510B

necting the Carry Out to the Carry In of the next stage while clocking each cou nter in parallel. The outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the Reset (R) pin. T his CMOS counter finds primary use in u p/down and difference counting. Other a pplications include: (1) Frequency synt hesizer applications where low power di ssipation and/or h.



Part

MC14510B

Description

BCD Up/Down Counter

Manufacture

Motorola

Datasheet
Download MC14510B Datasheet




 MC14510B
MOTOROLA
www.DSatEaSMhIeCetO4UN.cDoUmCTOR TECHNICAL DATA
MC14510B
BCD Up/Down Counter
The MC14510B synchronous up/down BCD counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure. The counter consists of type D flip–flop stages with a gating
structure to provide type T flip–flop capability.
This counter can be preset by applying the desired value in BCD to the
Preset inputs (P1, P2, P3, P4) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q1, Q2, Q3, Q4) can be reset to a low state by applying a high to the
Reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
Asynchronous Preset Enable Operation
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapable of Driving Two Low–power TTL Loads or One Low–power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchottky TTL Load Over the Rated Temperature Range.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA
per Pin
PD Power Dissipation, per Package†
500 mW
Tstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature (8–Second Soldering)
260 _ C
* Maximum Ratings are those values beyond which damage to the may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_ C From 65_ C To 125_ C
Ceramic “L” Packages: – 12 mW/_ C From 100_ C To 125_ C
TRUTH TABLE
Preset
Carry In Up/Down Enable
Reset
Clock
Action
1 X 0 0 X No Count
0 1 00
Count Up
0 0 00
Count Down
X X 10X
Preset
X X X1X
Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high, and is low only
when Q1 and Q4 are high and Carry In is low. When counting down, Carry
Out is low only when Q1 through Q4 and Carry In are low.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
1 PE
Q1 6
5 CARRY IN
9R
Q2 11
10 UP/DOWN
15 CLOCK Q3 14
4 P1
12 P2
Q4 2
13 P3
3
P4
CARRY
OUT
7
VDD = PIN 16
VSS = PIN 8
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
MC14510B
351





 MC14510B
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Characteristic
Symbol Vdc
Min
Max
Min
Typ #
Max
Min
Max Unit
Output Voltage
Vin = VDD or 0
“0” Level VOL
5.0
0.05
10 — 0.05 —
15 — 0.05 —
0 0.05 — 0.05 Vdc
0 0.05 — 0.05
0 0.05 — 0.05
Vin = 0 or VDD
“1” Level VOH
5.0 4.95 — 4.95
10 9.95 — 9.95
15 14.95 — 14.95
5.0
10
15
— 4.95 — Vdc
— 9.95 —
— 14.95 —
Input Voltage
“0” Level VIL
Vdc
(VO = 4.5 or 0.5 Vdc)
5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc)
10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc)
15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH
Vdc
(VO = 0.5 or 4.5 Vdc)
5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc)
10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc)
15 11 — 11 8.25 — 11 —
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
IOH
5.0 – 3.0
– 2.4
– 4.2
5.0 – 0.64 — – 0.51 – 0.88
10 – 1.6 — – 1.3 – 2.25
15 – 4.2
– 3.4
– 8.8
mAdc
— – 1.7 —
— – 0.36 —
— – 0.9 —
— – 2.4 —
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
Sink IOL
Iin
Cin
IDD
5.0 0.64 — 0.51 0.88
10 1.6 — 1.3 2.25
15 4.2 — 3.4
8.8
— 0.36 — mAdc
— 0.9 —
— 2.4 —
15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
—— — —
5.0
7.5 —
— pF
5.0
5.0
0.005
5.0
150 µAdc
10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT 5.0
10
15
IT = (0.58 µA/kHz) f + IDD
IT = (1.20 µA/kHz) f + IDD
IT = (1.70 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_ C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
PE
Q4
P4
P1
CARRY IN
Q1
CARRY OUT
VSS
1
2
3
4
5
6
7
8
16 VDD
15 C
14 Q3
13 P3
12 P2
11 Q2
10 U/D
9R
MC14510B
352
MOTOROLA CMOS LOGIC DATA





 MC14510B
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Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Symbol
tTLH,
tTHL
tPLH,
tPHL
VDD
5.0
10
15
5.0
10
15
Min Typ # Max Unit
ns
— 100 200
— 50 100
— 40 80
ns
— 315 630
— 130 260
— 100 200
Clock to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
ns
tPHL 5.0 — 315 630
10 — 130 260
15 — 100 200
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 47 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
tPLH,
ns
tPHL 5.0 — 180 360
10 — 80 160
15 — 60 120
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
Reset Pulse Width
tPLH,
tPHL
tPLH,
tPHL
tw(H)
ns
5.0 — 315 630
10 — 130 260
15 — 100 200
ns
5.0 — 550 1100
10 — 225 450
15 — 150 300
5.0 360 180
10 210 105
15 160 80
— ns
Clock Pulse Width
tw(H)
5.0 350 200
10 170 100
15 140 75
— ns
Clock Pulse Frequency
fcl 5.0 — 3.0 1.5 MHz
10 — 6.0 3.0
15 — 8.0 4.0
Preset or Reset Removal Time
The Preset or Reset Signal must be low prior to a
positive–going transition of the clock.
trem
5.0 650 325
10 230 115
15 180 90
— ns
Clock Rise and Fall Time
tTLH,
5.0
15 µs
tTHL 10 — —
5
15 — —
4
Setup Time
Carry In to Clock
tsu
5.0 260 130
— ns
10 120 60
15 100 50
Hold Time
Clock to Carry In
th 5.0 0 – 50 — ns
10 10 – 15 —
15 10 – 5 —
Setup Time
Up/Down to Clock
tsu
5.0 500 250
— ns
10 200 100 —
15 175 75
Hold Time
Clock to Up/Down
th 5.0 – 70 – 140 — ns
10 – 30 – 80 —
15 – 20 – 50 —
Setup Time
Pn to PE
tsu 5.0 – 50 – 100 — ns
10 – 30 – 65 —
15 – 25 – 55 —
Hold Time
PE to Pn
th
5.0 480 240
— ns
10 410 205 —
15 410 205 —
Preset Enable Pulse Width
tWH
5.0 200 100
— ns
10 100 50
15 80 40 —
* The formulas given are for the typical characteristics only at 25_ C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14510B
353



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