(CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Description
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CY7C1471V33 CY7C1473V33 CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and funct...
