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HD6475348. 6475348 Datasheet

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HD6475348. 6475348 Datasheet






6475348 HD6475348. Datasheet pdf. Equivalent




6475348 HD6475348. Datasheet pdf. Equivalent





Part

6475348

Description

HD6475348



Feature


OMC 932723248 www.DataSheet4U.com Hitac hi Single-Chip Microcomputer H8/534, H8 /536 HD6475348R, HD6435348R HD6475368R, HD6435368R HD6475348S, HD6435348S HD64 75368S, HD6435368S Hardware Manual ADE -602-038B Preface www.DataSheet4U.com The H8/534 and H8/536 are high-perform ance single-chip Hitachi-original micro computers, featuring a high-speed CPU w ith 16-bit interna.
Manufacture

Hitachi Semiconductor

Datasheet
Download 6475348 Datasheet


Hitachi Semiconductor 6475348

6475348; l data paths and a full complement of on -chip supporting modules. They are idea l microcontrollers for a wide variety o f medium-scale devices, including both office and industrial equipment and con sumer products. The CPU has a general-r egister architecture. Its instruction s et is highly orthogonal and is optimize d for fast execution of programs coded in the high-level .


Hitachi Semiconductor 6475348

C language. For further speed, the exist ing 10-MHz lineup has been extended to include high-speed versions that operat e at 16 MHz. Low-voltage versions that operate at 3 V and 2.7 V have also been developed. On-chip facilities include large RAM and ROM memories, numerous ti mers, serial I/O, an A/D converter, I/O ports, and other functions for compact implementation of.


Hitachi Semiconductor 6475348

high-performance application systems. H 8/534 and H8/536 are available in both a ZTAT™ version* with on-chip PROM, i deal for the early stages of production or for products with frequently-changi ng specifications, and a maskedROM vers ion suitable for volume production. Thi s manual gives a hardware description o f the H8/534 and H8/536. For details of the instruction set.

Part

6475348

Description

HD6475348



Feature


OMC 932723248 www.DataSheet4U.com Hitac hi Single-Chip Microcomputer H8/534, H8 /536 HD6475348R, HD6435348R HD6475368R, HD6435368R HD6475348S, HD6435348S HD64 75368S, HD6435368S Hardware Manual ADE -602-038B Preface www.DataSheet4U.com The H8/534 and H8/536 are high-perform ance single-chip Hitachi-original micro computers, featuring a high-speed CPU w ith 16-bit interna.
Manufacture

Hitachi Semiconductor

Datasheet
Download 6475348 Datasheet




 6475348
OMC 932723248
www.DataSheet4U.com
Hitachi Single-Chip Microcomputer
H8/534, H8/536
HD6475348R, HD6435348R
HD6475368R, HD6435368R
HD6475348S, HD6435348S
HD6475368S, HD6435368S
Hardware Manual
ADE-602-038B




 6475348
www.DataSheet4U.com
Preface
The H8/534 and H8/536 are high-performance single-chip Hitachi-original microcomputers,
featuring a high-speed CPU with 16-bit internal data paths and a full complement of on-chip
supporting modules. They are ideal microcontrollers for a wide variety of medium-scale devices,
including both office and industrial equipment and consumer products.
The CPU has a general-register architecture. Its instruction set is highly orthogonal and is
optimized for fast execution of programs coded in the high-level C language. For further speed,
the existing 10-MHz lineup has been extended to include high-speed versions that operate at
16 MHz. Low-voltage versions that operate at 3 V and 2.7 V have also been developed.
On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D
converter, I/O ports, and other functions for compact implementation of high-performance
application systems.
H8/534 and H8/536 are available in both a ZTATversion* with on-chip PROM, ideal for the
early stages of production or for products with frequently-changing specifications, and a masked-
ROM version suitable for volume production.
This manual gives a hardware description of the H8/534 and H8/536. For details of the instruction
set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500
Series.
* ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
2




 6475348
Contents
www.DataSheet4U.com
Section 1 Overview
1.1 Features ··································································································································1
1.2 Block Diagram ·······················································································································5
1.3 Pin Arrangements and Functions ···························································································6
1.3.1 Pin Arrangement ·········································································································6
1.3.2 Pin Functions ··············································································································9
Section 2 MCU Operating Modes and Address Space
2.1 Overview ······························································································································23
2.2 Mode Descriptions ···············································································································24
2.3 Address Space Map ··············································································································25
2.3.1 Page Segmentation ····································································································25
2.3.2 Page 0 Address Allocations ······················································································26
2.4 Mode Control Register (MDCR) ·························································································27
Section 3 CPU
3.1 Overview ······························································································································31
3.1.1 Features ·····················································································································31
3.1.2 Address Space ···········································································································32
3.1.3 Register Configuration ······························································································33
3.2 CPU Register Descriptions ··································································································34
3.2.1 General Registers ······································································································34
3.2.2 Control Registers ······································································································35
3.2.3 Initial Register Values ·······························································································40
3.3 Data Formats ························································································································41
3.3.1 Data Formats in General Registers ···········································································41
3.3.2 Data Formats in Memory ··························································································42
3.4 Instructions ···························································································································44
3.4.1 Basic Instruction Formats ·························································································44
3.4.2 Addressing Modes ····································································································45
3.4.3 Effective Address Calculation ··················································································47
3.5 Instruction Set ······················································································································50
3.5.1 Overview ···················································································································50
3.5.2 Data Transfer Instructions ·························································································52
3.5.3 Arithmetic Instructions ·····························································································53
3.5.4 Logic Operations ·······································································································54
3.5.5 Shift Operations ········································································································55
3.5.6 Bit Manipulations ······································································································56
3.5.7 Branching Instructions ······························································································57



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