Edge-Triggered Flip-Flops. 54LS374 Datasheet

54LS374 Flip-Flops. Datasheet pdf. Equivalent

54LS374 Datasheet
Recommendation 54LS374 Datasheet
Part 54LS374
Description TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
Feature 54LS374; DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggere.
Manufacture National Semiconductor
Datasheet
Download 54LS374 Datasheet




National Semiconductor 54LS374
May 1992
DM54LS373 DM74LS373
DM54LS374 DM74LS374
TRI-STATE Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
www.DataSheet4U.com
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relative-
ly low-impedance loads The high-impedance state and in-
creased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components They are particularly attractive
for implementing buffer registers I O ports bidirectional
bus drivers and working registers
(Continued)
Features
Y Choice of 8 latches or 8 D-type flip-flops in a single
package
Y TRI-STATE bus-driving outputs
Y Full parallel-access for loading
Y Buffered control inputs
Y P-N-P inputs reduce D-C loading on data lines
Connection Diagrams
Dual-In-Line Packages
’LS373
Order Number
DM54LS373J
DM54LS373W
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A M20B N20A or
W20A
’LS374
TL F 6431 – 1
Order Number
DM54LS374J
DM54LS374W
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A M20B N20A or
W20A
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL F 6431
TL F 6431 – 2
RRD-B30M105 Printed in U S A



National Semiconductor 54LS374
General Description (Continued)
The eight latches of the DM54 74LS373 are transparent D-
type latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs When the enable is
taken low the output will be latched at the level of the data
that was set up
The eight flip-flops of the DM54 74LS374 are edge-trig-
gered D-type flip flops On the positive transition of the
clock the Q outputs will be set to the logic states that were
set up at the D inputs
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state In the high-impedance
state the outputs neither load nor drive the bus lines signifi-
cantly
The output control does not affect the internal operation of
the latches or flip-flops That is the old data can be retained
or new data can be entered even while the outputs are off
Function Tables
DM54 74LS373
DM54 74LS374
Output
Enable D Output
Control
G
www.DataSheet4U.com L
HHH
L HLL
L L X Q0
H XXZ
Output Clock D Output
Control
L
uH
H
L
uL
L
L L X Q0
H
XX
Z
H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care
u e Transition from low-to-high level Z e High Impedance State
Q0 e The level of the output before steady-state input conditions were established
Logic Diagrams
DM54 74LS373
Transparent Latches
DM54 74LS374
Positive-Edge-Triggered Flip-Flops
TL F 6431–3
2
TL F 6431 – 4



National Semiconductor 54LS374
Absolute Maximum Ratings (See Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
7V
Storage Temperature Range
b65 C to a150 C
Operating Free Air Temperature Range
DM54LS
b55 C to a125 C
DM74LS
0 C to a70 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
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Recommended Operating Conditions
Symbol
Parameter
DM54LS373
Min Nom
VCC Supply Voltage
45 5
VIH High Level Input Votage
2
VIL Low Level Input Voltage
IOH High Level Output Current
IOL Low Level Output Current
tW
Pulse Width
Enable High
15
(Note 2)
Enable Low
15
vtSU
Data Setup Time (Notes 1 2)
5
vtH
Data Hold Time (Notes 1 2)
20
TA
Free Air Operating Temperature
b55
vNote 1 The symbol ( ) indicates the falling edge of the clock pulse is used for reference
Note 2 TA e 25 C and VCC e 5V
Max
55
07
b1
12
125
’LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
VOH
VOL
II
IIH
IIL
IOZH
IOZL
IOS
ICC
Parameter
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
High Level Input Current
Low Level Input Current
Off-State Output Current
with High Level Output
Voltage Applied
Off-State Output Current
with Low Level Output
Voltage Applied
Short Circuit
Output Current
Supply Current
Conditions
VCC e Min II e b18 mA
VCC e Min
IOH e Max
VIL e Max
VIH e Min
VCC e Min
IOL e Max
VIL e Max
VIH e Min
IOL e 12 mA
VCC e Min
VCC e Max VI e 7V
VCC e Max VI e 2 7V
VCC e Max VI e 0 4V
VCC e Max VO e 2 7V
VIH e Min VIL e Max
VCC e Max VO e 0 4V
VIH e Min VIL e Max
VCC e Max
(Note 2)
VCC e Max OC e 4 5V
Dn Enable e GND
DM54
DM74
DM54
DM74
DM74
DM54
DM74
Min
4 75
2
15
15
5v
20v
0
DM74LS373
Nom
5
Max
5 25
08
b2 6
24
70
Min
Typ
(Note 1)
Max
b1 5
24 34
24 31
0 25 0 4
0 35 0 5
04
01
20
b0 4
20
b20
b20
b50
b100
b225
24 40
Units
V
V
V
mA
mA
ns
ns
ns
C
Units
V
V
V
mA
mA
mA
mA
mA
mA
mA
3







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