TSPC603R PID7t-603e Datasheet

TSPC603R Datasheet, PDF, Equivalent


Part Number

TSPC603R

Description

PowerPC 603e RISC Microprocessor Family PID7t-603e

Manufacture

ATMEL

Total Page 30 Pages
Datasheet
Download TSPC603R Datasheet


TSPC603R
Features
Superscalar (3 Instructions per Clock Peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On-chip Debug Support
Nap, Doze and Sleep Power Saving Modes
Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
www.DataShPeDet4TUyp.ciocmally = 3.5W (266 MHz), Full Operating Conditions
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4-Gbytes Direct Addressing Range
Pipelined Single/Double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
fINT Max = 300 MHz
fBUS Max = 75 MHz
Compatible CMOS Input/TTL Output
Features Specific to Cerquad
5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
PD Typically = 2.5W (200 MHz), Full Operating Conditions
1. Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a
low-power implementation of the Reduced Instruction Set Computer (RISC) micropro-
cessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e
and 603P in a Cerquad package. The 603R implements 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable
power-saving modes. This device is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions can be executed in any
order for increased performance, but, the 603R makes completion appear sequential.
It integrates five execution units and is able to execute five instructions in parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physi-
cally addressed caches for instructions and data, as well as on-chip instructions, and
data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way
set-associative, data and instruction translation look aside buffers that provide support
for demand-paged virtual memory address translation and variable-sized block trans-
lation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The
interface protocol allows multiple masters to compete for system resources through a
central external arbiter. The device supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/Os.
PowerPC® 603e
RISC
Microprocessor
Family
PID7t-603e
TSPC603R
Rev. 5410B–HIREL–09/05

TSPC603R
The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface
compatibility with TTL devices. It also integrates in-system testability and debugging features
through JTAG boundary-scan capabilities.
2. Screening/Quality/Packaging
This product is manufactured in full compliance with:
www.DataSheet4U.com
• HiTCE CBGA according to Atmel Standards
• CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to Atmel standards
• CBGA 255: Upscreenings based upon Atmel standards
• CBGA, CI-CGA, HiTCE packages:
– Full military temperature range (TC = -55°C, Tj = +125°C)
– Industrial temperature range (TC = -40°C, Tj = +110°C)
• Cerquad:
– Full military temperature range (TC = -55°C, Tc = +125°C)
– Industrial temperature range (TC = -40°C, Tc = +110°C)
– Commercial temperature ranges (TC = 0°C, TC = +70°C)
• Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5%
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity up
G suffix
CBGA 255
Ceramic Ball Grid Array
GS suffix
CI-CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
CERQUAD 240
GH suffix
HiTCE 255
Ceramic Ball Grid Array
2 TSPC603R
5410B–HIREL–09/05


Features Features • • • • • • • Sup erscalar (3 Instructions per Clock Peak ) Dual 16 KB Caches Selectable Bus Cloc k 32-bit Compatibility PowerPC Implemen tation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Off ered in Cerquad, CBGA 255, HiTCE CBGA 2 55 and CI-CGA 255 Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 25 5 • 7.4 SPECint95, 6.1 SPECfp95 at 30 0 MHz (Estimated) • PD Typically = 3. 5W (266 MHz), Full Operating Conditions www.DataSheet4U.com • Branch Folding • 64-bit Data Bus (32-bit Data Bus O ption) • 4-Gbytes Direct Addressing R ange • Pipelined Single/Double Precis ion Float Unit • IEEE 754 Compatible FPU • IEEE P 1149-1 Test Mode (JTAG/C 0P) • fINT Max = 300 MHz • fBUS Max = 75 MHz • Compatible CMOS Input/TTL Output PowerPC® 603e RISC Microproce ssor Family PID7t-603e TSPC603R Featur es Specific to Cerquad • 5.6 SPECint9 5, 4 SPECfp95 and 200 MHz (Estimated) PD Typically = 2.5W (200 MHz), Full Operating Conditions 1. Description The PID7t-603e implementatio.
Keywords TSPC603R, datasheet, pdf, ATMEL, PowerPC, 603e, RISC, Microprocessor, Family, PID7t-603e, SPC603R, PC603R, C603R, TSPC603, TSPC60, TSPC6, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)