10EL34 Datasheet (data sheet) PDF

10EL34 Datasheet, MC10EL34

10EL34   10EL34  

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA ÷2, ÷4, ÷8 Clock MC10EL34 MC100EL3 4 Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generat ion chip designed explicitly for low sk ew clock generation applications. The i nternal dividers are synchronous to eac h other, therefore, the common output e dges are all precisely aligned. The dev ice can be driven by either a different ial or single-ended ECL or, if positive power supplies are used, PECL input si gnal. In addition, by using the VBB out put, a sinusoidal source can be AC coup led into the device (see Interfacing se ction of the www.DataSheet4U.com ECLinP S™ Data Book DL140/D). If a sin

10EL34 Datasheet, MC10EL34

gle-ended input is to be used, the VBB o utput should be connected to the CLK in put and bypassed to ground via a 0.01µ F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ende d input conditions, as a result, this p in can only source/sink up to 0.5mA of current. The common enable (EN) is sync hronous so that the internal dividers w ill only be enabled/disabled when the i nternal clock is already in the LOW sta te. This avoids any chance of generatin g a runt clock pulse on the internal cl ock when the device is enabled/disabled as can happen with an asynchronous con trol. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal e nable flip-flop is clocked on the falli ng edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the interna l flip-flops will attain a random state ; the master reset (MR) input allows fo r the synchronization of the internal d ividers, as well as multiple EL34s in a system. 16 1 D SUFFIX PLASTIC SOIC P ACKAGE CASE 751B-05 PIN DESCRIPTION PI N CLK EN MR VBB Q0 Q1 Q2 FUNCTION Diff Clock Inputs Sync Enable Master Reset R eference Output Diff ÷2 Outputs Diff ÷4 Outputs Diff

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