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CY7C1410V18

Part Number	CY7C1410V18
Manufacturer	Cypress Semiconductor
Description	(CY7C14xxV18) SRAM 2-Word Burst Architecture
Published	Jul 23, 2008
Detailed Description	PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • ...
Datasheet	CY7C1410V18 PDF File

Overview

PRELIMINARY CY7C1410V18 CY7C1425V18 CY7C1412V18 CY7C1414V18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 200-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz www.
DataSheet4U.
com • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Re...

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CY7C1410V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture - Cypress Semiconductor

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