Zero Delay. CY29351 Datasheet

CY29351 Delay. Datasheet pdf. Equivalent

Part CY29351
Description 9-Output Zero Delay
Feature PRELIMINARY CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Features ■ ■ ■ ■ Functional Descrip.
Manufacture Cypress Semiconductor
Datasheet
Download CY29351 Datasheet




CY29351
PRELIMINARY
CY29351
2.5V or 3.3V, 200 MHz,
9-Output Zero Delay
Features
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
www.DataShee±t24.U5.%commax Output duty cycle variation
9 clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread Aware™
Output enable/disable
Pin-compatible with MPC9351
Industrial temperature range: –40°C to +85°C
32-pin 1.0-mm TQFP package
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in four banks of one,
one, two, and five outputs. Bank A divides the VCO output by two
or four while the other banks divide by four or eight per SEL(A:D)
settings (Table 3, “Function Table,” on page 3). These dividers
allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each
LVCMOS compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated trans-
mission lines, each output can drive one or two traces giving the
device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider (Table 2,
“Frequency Table,” on page 3).
When PLL_EN# is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
PECL_CLK
Phase
Detector
VCO
200 -
500 MHz
LPF
÷2 / ÷4
÷4 / ÷8
QA
QB
FB_IN
SELB
SELC
OE#
SELD
÷4 / ÷8
÷4 / ÷8
QC0
QC1
QD0
QD1
QD2
QD3
QD4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07475 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 21, 2008
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CY29351
Pinouts
www.DataSheet4U.com
PRELIMINARY
Figure 1. Pin Diagram - 32 Pin TQFP Package
AVDD
FB_IN
SELA
SELB
SELC
SELD
AVSS
PECL_CLK
1 24 QC0
2 23 VDDQC
3 22 QC1
4
5
CY29351
21
20
VSS
QD0
6 19 VDDQD
7 18 QD1
8 17 VSS
CY29351
Table 1. Pin Definitions - 32 Pin TQFP Package
Pin[1]
Name
IO Type
Description
8 PECL_CLK I, PU LVPECL LVPECL reference clock input
9 PECL_CLK# I, PU/PD LVPECL LVPECL reference clock input. Weak pull up to VDD/2.
30
TCLK
I, PD LVCMOS LVCMOS/LVTTL reference clock input
28 QA O LVCMOS Clock output bank A
26 QB O LVCMOS Clock output bank B
22, 24
QC(1,0)
O LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O LVCMOS Clock output bank D
2
FB_IN
I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock
10
OE#
I, PD LVCMOS Output enable/disable input
31
PLL_EN
I, PU LVCMOS PLL enable/disable input
32
REF_SEL
I, PD LVCMOS Reference select input
3, 4, 5, 6
27
23
15, 19
1
11
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
I, PD
Supply
Supply
Supply
Supply
Supply
LVCMOS Frequency select input, bank (A:D)
VDD 2.5V or 3.3V power supply for bank B output clock[2,3]
VDD 2.5V or 3.3V power supply for bank C output clocks[2,3]
VDD 2.5V or 3.3V power supply for bank D output clocks[2,3]
VDD 2.5V or 3.3V power supply for PLL[5,6]
VDD 2.5V or 3.3V power supply for core, inputs, and bank A output clock[2,3]
7
AVSS
Supply Ground Analog ground
13, 17, 21, 25, 29 VSS
Supply Ground Common ground
Notes
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the
high-frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing
is within the VPP (DC) specification.
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission
lines.
6. Inputs have pull up or pull down resistors that affect the input current.
Document Number: 38-07475 Rev. *B
Page 2 of 10
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