Parallel Port Adapter
§ Provides a parallel port interface for Dallas iButtons
§ Compatible with low-power parallel ports
§ No external power required
§ Operates with DOS, Windows, Windows 95, Windows
NT, SCO UNIX, UNIXWARE, and HP_UX for
The DS1410E Parallel Port Adapter interfaces Dallas Semiconductor Authorization iButtons to host
computers via a PC parallel port. In conjunction with the iButton, the DS1410E provides a high security
storage vault for critical execution control information. Only users who posses an iButton can utilize the
software, preventing execution of unauthorized copies.
The modularity of the DS1994 allows for easy feature customization. The device supports the insertion of
two iButtons, which can be removed and replaced to vary functionality.
For example, a DS1994 Time iButton can be programmed for a 30-day expiration, issued with a
DS1410E and a software copy. The evaluator can be converted into a registered user by issuing a DS1991
Multi iButton and inserting it into the second receptacle. The DS1410E supports the same iButtons as
other Dallas port adapters. This allows standardization of any protection scheme across virtually all
hardware platforms, regardless of the operating system. The iButtons remain constant, and the port
adapters change according to the specific platform interface.
The DS1410k Development Kit contains access system software which must be linked with the
application software in order to complete integration. The support for the application development
environments and operating systems lies in the interface software of the access system. The access system
contains the low-level interface for communicating with the iButtons.
The DS1410E utilizes a DS1481 1-WireTM Bus Master to communicate with iButtons. The DS1481
generates either a read/write bit “time slot” or a reset on the I/O pin (1-Wire bus). The operation
performed is determined by the states of input pins 2 and 3 on the port adapter as follows:
Read 0, Read1, Write 1
logic high(see Figure 1)
logic high (see Figure 2)
logic low (See Figure 3)
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