ADS5421 Datasheet PDF Download, Burr-Brown Corporation





(PDF) ADS5421 Datasheet Download

Part Number ADS5421
Description 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Manufacture Burr-Brown Corporation
Total Page 21 Pages
PDF Download Download ADS5421 Datasheet PDF

Features: ADS5421 ADS 542 1 SBAS237D – DECEMBER 2001 – REVISED JULY 2004 14-Bit, 40 MHz Sampling ANALOG-TO-DIGITAL CONVERTE R FEATURES q HIGH DYNAMIC RANGE: High S FDR: 83dB at 10MHz fIN www.DataSheet4U. com High SNR: 75dB at 10MHz f IN q PREM IUM TRACK-AND-HOLD: Differential Inputs Selectable Full-Scale Input Range q LO W POWER: 850mW q FLEXIBLE CLOCKING: Dif ferential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level DESCRIPTION The ADS5421 is a high-dynamic range 14- bit, 40MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-ba ndwidth linear track-and-hold amplifier that gives excellent spurious performa nce up to and beyond the Nyquist rate. The clock input can accept a low-level differential sine wave or square wave s ignal down to 0.5Vp-p, further improvin g the Signal-to-Noise Ratio (SNR) perfo rmance. The ADS5421 has a 4Vp-p differe ntial input range (2Vp-p • 2 inputs) for optimum Spurious-Free Dynamic Range (SFDR). The differential oper.

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ADS5421
ADS5421
SBAS237D – DECEMBER 2001 – REVISED JULY 2004
14-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH DYNAMIC RANGE:
High SFDR: 83dB at 10MHz fIN
www.DataSheet4U.com High SNR: 75dB at 10MHz f
IN
q PREMIUM TRACK-AND-HOLD:
Differential Inputs
Selectable Full-Scale Input Range
q LOW POWER: 850mW
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking Down to
0.5Vp-p
Variable Threshold Level
APPLICATIONS
q COMMUNICATIONS RECEIVERS
q TEST INSTRUMENTATION
q PROFESSIONAL CCD IMAGING
DESCRIPTION
The ADS5421 is a high-dynamic range 14-bit, 40MHz,
pipelined Analog-to-Digital Converter (ADC). It includes a
high-bandwidth linear track-and-hold amplifier that gives
excellent spurious performance up to and beyond the Nyquist
rate. The clock input can accept a low-level differential sine
wave or square wave signal down to 0.5Vp-p, further improving
the Signal-to-Noise Ratio (SNR) performance.
The ADS5421 has a 4Vp-p differential input range
(2Vp-p • 2 inputs) for optimum Spurious-Free Dynamic
Range (SFDR). The differential operation gives the lowest
even-order harmonic components. A lower input voltage can
also be selected using the internal references, further
optimizing SFDR.
The ADS5421 is available in a small LQFP-64 package.
1Vp-p
1Vp-p
ADS5421
IN
IN
CM
(+2.5V)
T&H
+VS
Timing Circuitry
14-Bit
Pipelined
ADC
Core
Error
Correction
Logic
DV
CLK
CLK
3-State
Outputs
D0
•••
D13
Reference Ladder
and Driver
Reference and
Mode Select
REFT
VREF SEL1 SEL2 REFB
OE VDRV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001-2004 Texas Instruments, Incorporated

                    
                    






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