71P71204S250BQ8 IDT71P71204S250BQ8 Datasheet
|Total Page||24 Pages|
Burst of 2
x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
x Common Read and Write Data Port
x Dual Echo Clock Output
x 2-Word Burst on all SRAM accesses
x Multiplexed Address Bus
- One Read or One Write request per clock cycle
www.DataSheet4U.coxm DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
x Depth expansion through Control Logic
x HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
x Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
x 1.8V Core Voltage (VDD)
x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
x JTAG Interface
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data trans-
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, indepen-
dent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the DDRII has an output “echo” clock,
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and BWx or NWx), the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
C SELECT OUTPUT CONTROL
6112 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6112/00
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The K clock is used to clock in the control signals (BWx or NWx), and the
second word of the data burst during a write operation. The K and K
clocks are also used internally by the SRAM. In the event that the user
disables the C and C clocks, the K and K clocks will also be used to clock
the data out of the output register and generate the echo clocks.
The C and C clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the C clock.
The C and second data word of the burst will also correspond.
www.DataSheeSt4iUn.gcolme Clock Mode
The DDRII SRAM may be operated with a single clock pair. C and C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and K clocks.
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding Doff low. With the DLL off, the C and C (or K and K
if C and C are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
The echo clocks, CQ and CQ, are generated by the C and C clocks
(or K, K if C, C are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of CQ. The rising edge of C generates
the rising edge of CQ and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing that
the echo clock will remain closely correlated with the data, within the
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and C clocks.
Write operations are initiated by holding the Read/Write control input
(R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BW or NW) inputs. On the follow-
ing rising edge of K, the second half of the data write burst will be
accepted at the device input with the designated (BW or NW) inputs.
DDRII devices internally store two words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9
DDRII devices do not have the ability to address to the single word
level or reverse the burst order; however the byte and nibble write
signals can be used to prevent writing any byte or individual nibbles,
or combined to prevent writing one word of the burst. The x18 and
x36 DDRll devices have the ability to address to the individual word
level using the SA0 address, but the burst will continue in a linear
sequence and wrap back on itself. The address will not increment to
the next higher burst address location, but instead will return to it’s
own lower words within the burst location. Similarly when reading x18
and x36 DDRll devices, the read burst will begin at the designated
address, but if the burst is started at any other position than the first
word of the burst, the burst will wrap back on itself and read the first
locations before completing.
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
|Features||18Mb Pipelined DDR™II SRAM Burst of 2 Features x x x x x www.DataSheet4U.com x x x x Advance Information IDT71P7120 4 IDT71P71104 IDT71P71804 IDT71P71604 Description The IDT DDRIITM Burst of tw o SRAMs are high-speed synchronous memo ries with a double-data-rate (DDR), bid irectional data port. This scheme allow s maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates a t single data rate speeds, allowing the user to fan out addresses and ease sys tem design while maintaining maximum pe rformance on data transfers. The DDRII has scalable output impedance on its da ta output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces o f the DDRII SRAM are HSTL, allowing spe eds beyond SRAM devices that use any fo rm of TTL interface. The interface can be scaled to higher voltages (up to 1.9 V) to interface with 1.8V systems if ne cessary. The device has a VDDQ and a separate Vref, allowing the .|
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