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Signal Array. CY8C24223 Datasheet

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Signal Array. CY8C24223 Datasheet






CY8C24223 Array. Datasheet pdf. Equivalent




CY8C24223 Array. Datasheet pdf. Equivalent





Part

CY8C24223

Description

(CY8C24x23) PSoC Mixed Signal Array



Feature


PSoC™ Mixed Signal Array CY8C24123, CY 8C24223, and CY8C24423 Final Data Shee t Features ■ Powerful Harvard Archit ecture Processor ❐ M8C Processor Spee ds to 24 MHz ❐ 8x8 Multiply, 32-Bit A ccumulate ❐ Low Power at High Speed 3.0 to 5.25 V Operating Voltage www. DataSheet4U.com ❐ Operating Voltages Down to 1.0V Using OnChip Switch Mode P ump (SMP) ❐ Industrial Temperatu.
Manufacture

Cypress Semiconductor

Datasheet
Download CY8C24223 Datasheet


Cypress Semiconductor CY8C24223

CY8C24223; re Range: -40°C to +85°C ■ Advanced Peripherals (PSoC Blocks) ❐ 6 Rail-to -Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 8-Bit DACs - Pro grammable Gain Amplifiers - Programmabl e Filters and Comparators ❐ 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Ti mers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART - Multiple S PI Masters or Slaves - Co.


Cypress Semiconductor CY8C24223

nnectable to all GPIO Pins ❐ Complex P eripherals by Combining Blocks ■ Prec ision, Programmable Clocking ❐ Intern al ±2.5% 24/48 MHz Oscillator ❐ High -Accuracy 24 MHz with Optional 32 kHz C rystal and PLL ❐ Optional External Os cillator, up to 24 MHz ❐ Internal Osc illator for Watchdog and Sleep ■ Flex ible On-Chip Memory ❐ 4K Bytes Flash Program Storage 50,000 Erase/Write .


Cypress Semiconductor CY8C24223

Cycles ❐ 256 Bytes SRAM Data Storage In-System Serial Programming (ISSP ) ❐ Partial Flash Updates ❐ Flexib le Protection Modes ❐ EEPROM Emulatio n in Flash ■ Programmable Pin Configu rations ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 10 Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configura.

Part

CY8C24223

Description

(CY8C24x23) PSoC Mixed Signal Array



Feature


PSoC™ Mixed Signal Array CY8C24123, CY 8C24223, and CY8C24423 Final Data Shee t Features ■ Powerful Harvard Archit ecture Processor ❐ M8C Processor Spee ds to 24 MHz ❐ 8x8 Multiply, 32-Bit A ccumulate ❐ Low Power at High Speed 3.0 to 5.25 V Operating Voltage www. DataSheet4U.com ❐ Operating Voltages Down to 1.0V Using OnChip Switch Mode P ump (SMP) ❐ Industrial Temperatu.
Manufacture

Cypress Semiconductor

Datasheet
Download CY8C24223 Datasheet




 CY8C24223
PSoC™ Mixed Signal Array
Final Data Sheet
CY8C24123, CY8C24223, and CY8C24423
Features
Powerful Harvard Architecture Processor
M8C Processor Speeds to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
www.DataSheet4U3.c.0otmo 5.25 V Operating Voltage
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
6 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 8-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART
- Multiple SPIMasters or Slaves
- Connectable to all GPIO Pins
Complex Peripherals by Combining Blocks
Precision, Programmable Clocking
Internal ±2.5% 24/48 MHz Oscillator
High-Accuracy 24 MHz with Optional 32 kHz
Crystal and PLL
Optional External Oscillator, up to 24 MHz
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
4K Bytes Flash Program Storage 50,000
Erase/Write Cycles
256 Bytes SRAM Data Storage
In-System Serial Programming (ISSP)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
Programmable Pin Configurations
25 mA Sink on all GPIO
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
Up to 10 Analog Inputs on GPIO
Two 30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
Additional System Resources
I2CSlave, Master, and Multi-Master to
400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Integrated Supervisory Circuit
On-Chip Precision Voltage Reference
Complete Development Tools
Free Development Software
(PSoC™ Designer)
Full-Featured, In-Circuit Emulator and
Programmer
Full Speed Emulation
Complex Breakpoint Structure
128K Bytes Trace Memory
PSoC CORE
Port 2
Port 1
Port 0
Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
Interrupt
Controller
SROM Flash 4K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block Array
(1 Rows,
4 Blocks)
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref
(2 Columns,
6 Blocks)
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
Decimator
POR and LVD
I2C
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Switch
Mode
Pump
PSoC™ Functional Overview
The PSoC™ family consists of many Mixed Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C24x23 family can have up to three IO
ports that connect to the global digital and analog interconnects,
providing access to 4 digital blocks and 6 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
June 2004
© Cypress MicroSystems, Inc. 2004 — Document No. 38-12011 Rev. *F
1




 CY8C24223
CY8C24x23 Final Data Sheet
PSoC™ Overview
processor. The CPU utilizes an interrupt controller with 11 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 4 KB of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash utilizes four protec-
tion levels on blocks of 64 bytes, allowing customized software
IP protection.
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 2.5% over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
www.DataShpeoewt4eUr.c3o2mkHz ILO (internal low speed oscillator) is provided for
the Sleep timer and WDT. If crystal accuracy is desired, the
ECO (32.768 kHz external crystal oscillator) is available for use
as a Real Time Clock (RTC) and can optionally generate a crys-
tal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfac-
ing. Every pin also has the capability to generate a system inter-
rupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Port 2
Port 1
Port 0
8
8
Digital Clocks To System Bus To Analog
From Core
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBB00 DBB01 DCB02 DCB03
4
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity (up to 1)
SPI master and slave (up to 1)
I2C slave and master (1 available as a System Resource)
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA (up to 1)
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and
can be customized to support specific application requirements.
Some of the more common PSoC analog functions (most avail-
able as user modules) are listed below.
Analog-to-digital converters (up to 2, with 6- to 14-bit resolu-
tion, selectable as Incremental, Delta Sigma, and SAR)
Filters (2 and 4 pole band-pass, low-pass, and notch)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (up to 2, with 16 selectable thresholds)
DACs (up to 2, with 6- to 9-bit resolution)
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
High current output drivers (two with 30 mA drive as a Core
Resource)
1.3V reference (as a System Resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
Digital System Block Diagram
June 4, 2004
Document No. 38-12011 Rev. *F
2




 CY8C24223
CY8C24x23 Final Data Sheet
PSoC™ Overview
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks. The number of blocks is dependant on the device family
which is detailed in the table titled “PSoC Device Characteris-
tics” on page 3.
P0[7]
P0[5]
P0[3]
P0[1]
www.DataSheet4U.cPo2m[3]
P2[1]
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
Interface to
Digital System
RefHi
RefLo
AGND
Analog Reference
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Analog System Block Diagram
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Addi-
tional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief state-
ments describing the merits of each system resource are pre-
sented below.
Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
3 analog blocks. The following table lists the resources
available for specific PSoC device groups.
PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C27x66
CY8C27x43
CY8C24x23
CY8C22x13
up to
64
up to
44
up to
44
up to
24
up to
16
4
2
2
1
1
16 12
8 12
8 12
4 12
48
4
4
4
2
1
4 12
4 12
4 12
26
13
June 4, 2004
Document No. 38-12011 Rev. *F
3



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