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TG Converter. HD49335HNP Datasheet

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TG Converter. HD49335HNP Datasheet






HD49335HNP Converter. Datasheet pdf. Equivalent






HD49335HNP Converter. Datasheet pdf. Equivalent


HD49335HNP

Part

HD49335HNP

Description

CDS/PGA & 10-bit A/D TG Converter



Feature


HD49335NP/HNP CDS/PGA & 10-bit A/D TG Co nverter REJ03F0097-0100Z Rev.1.0 Feb.12 .2004 Description The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing system s together with a 10-bit A/D converter and timing generator in a single chip. www.DataSheet4U.com if examining There are address map a.
Manufacture

Renesas Technology

Datasheet
Download HD49335HNP Datasheet


Renesas Technology HD49335HNP

HD49335HNP; nd timing generator charts besides this specification. May be contacted to our sales department the details. Function s • • • • • • • Correlate d double sampling PGA Serial interface control 10-bit ADC Timing generator Ope rates using only the 3 V voltage Corres ponds to switching mode of power dissip ation and operating frequency Power dis sipation: 220 mW (Typ), maximum .


Renesas Technology HD49335HNP

frequency: 36 MHz (HD49335HNP) Power dis sipation: 150 mW (Typ), maximum frequen cy: 25 MHz (HD49335NP) • ADC direct i nput mode • QFN 64-pin package Featu res • Suppresses low-frequency noise, which output from CCD by the correlate d double sampling. • The S/H response frequency characteristics for the refe rence level can be adjusted using value s of external parts and re.

Part

HD49335HNP

Description

CDS/PGA & 10-bit A/D TG Converter



Feature


HD49335NP/HNP CDS/PGA & 10-bit A/D TG Co nverter REJ03F0097-0100Z Rev.1.0 Feb.12 .2004 Description The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing system s together with a 10-bit A/D converter and timing generator in a single chip. www.DataSheet4U.com if examining There are address map a.
Manufacture

Renesas Technology

Datasheet
Download HD49335HNP Datasheet




 HD49335HNP
HD49335NP/HNP
CDS/PGA & 10-bit A/D TG Converter
REJ03F0097-0100Z
Rev.1.0
Feb.12.2004
Description
The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.
There are address map and timing generator charts besides this specification. May be contacted to our sales department
www.DataSheet4Ui.fceoxmamining the details.
Functions
Correlated double sampling
PGA
Serial interface control
10-bit ADC
Timing generator
Operates using only the 3 V voltage
Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)
ADC direct input mode
QFN 64-pin package
Features
Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.
PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
High precision is provided by a 10-bit-resolution A/D converter.
Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization
(wave pattern). It is patented by Renesas.
Timing generator generates the all of pulse which are needed for CCD driving.
Rev.1.0, Feb.12.2004, page 1 of 29




 HD49335HNP
HD49335NP/HNP
Pin Arrangement
www.DataSheet4U.com
AVDD
BLKC
CDS_in
AVDD
BLKFB
BLKSH
AVSS
Test2
Test1
DLL_C
DVDD1
MON
41cont
CS
SDATA
SCK
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49 32
50 31
51 30
52 29
53 28
54 27
55 26
56 25
57 24
58 23
59 22
60 21
61 20
62 19
63 18
64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
XV3
XV2
XV1
DVDD3
DVDD4
1/4clk_o
H2A
DVSS4
DVSS4
1/2clk_o
H1A
DVDD4
DVDD3
RG
Reset
VD_in
(Top view)
Pin Description
Pin No.
1
2
3 to 12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Symbol
ID
DVSS1,2
D0 to D9
DVDD2
DVSS3
CLK_in
HD_in
VD_in
Reset
RG
DVDD3
DVDD4
H1A
1/2clk_o
DVSS4
DVSS4
H2A
1/4clk_o
DVDD4
DVDD3
Description
Odd/even number line detecting pulse output pin
CDS Digital ground + ADC output buffer ground (0 V)
Digital output (D0; LSB, D9; MSB)
ADC output buffer power supply (3 V)
General ground for TG (0 V)
CLK input (max 72 MHz)
HD input
VD input
Hardware reset (for DLL reset)
Reset gate pulse output
General power supply for TG (3 V)
H1 buffer power supply (3 V)
H.CCD transfer pulse output-1A
CLK_in 2 divided output. 3 divided output at 3 divided mode
H1 buffer ground (0 V)
H1 buffer ground (0 V)
H.CCD transfer pulse output-2A
CLK_in 4 divided output. 6 divided output at 3 divided mode
H2 buffer power supply (3 V)
General power supply for TG (3 V)
Rev.1.0, Feb.12.2004, page 2 of 29
Analog(A) or
I/O Digital(D)
Remarks
OD
2 mA/10 pF
—D
OD
2 mA/10 pF
—D
—D
ID
I/O D
I/O D
ID
Schmitt trigger
OD
3 mA/10 pF
—D
—D
OD
30 mA/165 pF
OD
2 mA/10 pF
—D
—D
OD
30 mA/165 pF
OD
2 mA/10 pF
—D
—D



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