65MSPS ADC. ADS5272 Datasheet
8-Channel, 12-Bit, 65MSPS ADC
with Serial LVDS Interface
SBAS324 − JUNE 2004
D Maximum Sample Rate: 65MSPS
D 12-Bit Resolution
D No Missing Codes
www.DataSheet4UD.comPower Dissipation: 996mW
D CMOS Technology
D Simultaneous Sample-and-Hold
D 70.5dB SNR at 10MHz IF
D Internal and External References
D 3.3V Digital/Analog Supply
D Serialized LVDS Outputs
D Integrated Frame and Synch Patterns
D MSB and LSB First Modes
D Option to Double LVDS Clock Output Currents
D Pin- and Format-Compatible Family
D TQFP-80 PowerPAD Package
D Portable Ultrasound Systems
D Tape Drives
D Test Equipment
D Optical Networking
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5272 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a TQFP-80 PowerPAD package and
is specified over a −40°C to +85°C operating range.
The ADS5272 is a high-performance, 65MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
Copyright 2004, Texas Instruments Incorporated
SBAS324 − JUNE 2004
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 2.7V
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA
Operating Free-Air Temperature Range, TA . . . . . . −40°C to 85°C
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 220°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
www.DataSheet4mUa.cyodmegrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
−40°C to +85°C
Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 4.69mm x 4.69mm (min), 6.20mm x 6.20mm (max).
SAMPLE RATE (MSPS)
RECOMMENDED OPERATING CONDITIONS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low Level Voltage Clock Input
High Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
(1) 6 × ADCLK.
VDD − 0.6
2.0VPP Internal Reference
Default with internal pull-up.
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
SBAS324 − JUNE 2004
TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Offset Temperature Coefficient
Fixed Attenuation in Channel(2)
Variable Attenuation in Channel(3)
Gain Temperature Coefficient(5)
ICC Total Supply Current
I(AVDD) Analog Supply Current
I(LVDD) Digital Output Driver Supply Current
Reference Top (internal)
Reference Bottom (internal)
VCM Output Current(6)
Reference Top (external)
Reference Bottom (external)
External Reference Input Current(7)
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overload Recovery Time
DIGITAL DATA OUTPUTS
Data Bit Rate
SCLK Serial Clock Input Frequency
Input Low Voltage
Input High Voltage
Input Pin Capacitance
MIN TYP MAX UNITS
fIN = 5MHz
fIN = 5MHz
REFT − REFB
VIN = FS, FIN = 5MHz
VIN = FS, FIN = 5MHz
VIN = FS, FIN = 5MHz, LVDS Into 100Ω Load
±50mV Change in Voltage
1.95 2.0 2.05
0.95 1.0 1.05
1.45 1.5 1.55
Differential Input Signal at 4VPP
Recovery to Within 1% of Code
VCM ± 0.05
4.0 CLK Cycles
340 780 MBPS
(1) Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
(2) Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation [VREF is defined
as (REFT − REFB)].
(3) Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
(4) The reference voltages are trimmed at production so that (VREFT − VREFB) is within ± 25mV of the ideal value of 1V. It does not include fixed attenuation.
(5) The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
(6) VCM provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of
the VCM buffer if loaded externally.
(7) Average current drawn from the reference pins in the external reference mode.